drm/i915: Track HAS_RPS alongside HAS_RC6 in the device info
For consistency (and elegance!), add intel_device_info.has_rps. The immediate boon is that RPS support is now emitted along the other capabilities in the debug log and after errors. Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk> Reviewed-by: Sagar Arun Kamble <sagar.a.kamble@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20190419134836.5626-1-chris@chris-wilson.co.uk
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@ -2585,6 +2585,8 @@ IS_SUBPLATFORM(const struct drm_i915_private *i915,
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#define HAS_RC6p(dev_priv) (INTEL_INFO(dev_priv)->has_rc6p)
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#define HAS_RC6pp(dev_priv) (false) /* HW was never validated */
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#define HAS_RPS(dev_priv) (INTEL_INFO(dev_priv)->has_rps)
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#define HAS_CSR(dev_priv) (INTEL_INFO(dev_priv)->display.has_csr)
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#define HAS_RUNTIME_PM(dev_priv) (INTEL_INFO(dev_priv)->has_runtime_pm)
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@ -370,6 +370,7 @@ static const struct intel_device_info intel_ironlake_m_info = {
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.has_llc = 1, \
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.has_rc6 = 1, \
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.has_rc6p = 1, \
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.has_rps = true, \
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.ppgtt_type = INTEL_PPGTT_ALIASING, \
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.ppgtt_size = 31, \
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I9XX_PIPE_OFFSETS, \
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@ -417,6 +418,7 @@ static const struct intel_device_info intel_sandybridge_m_gt2_info = {
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.has_llc = 1, \
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.has_rc6 = 1, \
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.has_rc6p = 1, \
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.has_rps = true, \
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.ppgtt_type = INTEL_PPGTT_FULL, \
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.ppgtt_size = 31, \
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IVB_PIPE_OFFSETS, \
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@ -470,6 +472,7 @@ static const struct intel_device_info intel_valleyview_info = {
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.num_pipes = 2,
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.has_runtime_pm = 1,
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.has_rc6 = 1,
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.has_rps = true,
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.display.has_gmch = 1,
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.display.has_hotplug = 1,
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.ppgtt_type = INTEL_PPGTT_FULL,
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@ -565,6 +568,7 @@ static const struct intel_device_info intel_cherryview_info = {
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.has_64bit_reloc = 1,
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.has_runtime_pm = 1,
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.has_rc6 = 1,
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.has_rps = true,
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.has_logical_ring_contexts = 1,
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.display.has_gmch = 1,
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.ppgtt_type = INTEL_PPGTT_FULL,
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@ -640,6 +644,7 @@ static const struct intel_device_info intel_skylake_gt4_info = {
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.has_runtime_pm = 1, \
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.display.has_csr = 1, \
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.has_rc6 = 1, \
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.has_rps = true, \
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.display.has_dp_mst = 1, \
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.has_logical_ring_contexts = 1, \
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.has_logical_ring_preemption = 1, \
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@ -118,6 +118,7 @@ enum intel_ppgtt_type {
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func(has_pooled_eu); \
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func(has_rc6); \
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func(has_rc6p); \
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func(has_rps); \
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func(has_runtime_pm); \
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func(has_snoop); \
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func(has_coherent_ggtt); \
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@ -7013,8 +7013,10 @@ static bool sanitize_rc6(struct drm_i915_private *i915)
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struct intel_device_info *info = mkwrite_device_info(i915);
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/* Powersaving is controlled by the host when inside a VM */
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if (intel_vgpu_active(i915))
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if (intel_vgpu_active(i915)) {
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info->has_rc6 = 0;
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info->has_rps = false;
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}
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if (info->has_rc6 &&
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IS_GEN9_LP(i915) && !bxt_check_bios_rc6_setup(i915)) {
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@ -8716,6 +8718,7 @@ void intel_enable_gt_powersave(struct drm_i915_private *dev_priv)
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if (HAS_RC6(dev_priv))
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intel_enable_rc6(dev_priv);
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if (HAS_RPS(dev_priv))
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intel_enable_rps(dev_priv);
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if (HAS_LLC(dev_priv))
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intel_enable_llc_pstate(dev_priv);
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