dmaengine: mediatek: Add MediaTek UART APDMA support
Add 8250 UART APDMA to support MediaTek UART. If MediaTek UART is enabled by SERIAL_8250_MT6577, and we can enable this driver to offload the UART device moving bytes. Signed-off-by: Long Cheng <long.cheng@mediatek.com> Signed-off-by: Sean Wang <sean.wang@mediatek.com> Signed-off-by: Vinod Koul <vkoul@kernel.org>
This commit is contained in:
Long Cheng
Vinod Koul
parent
2fe5575f36
commit
9135408c3a
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@ -24,3 +24,14 @@ config MTK_CQDMA
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This controller provides the channels which is dedicated to
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memory-to-memory transfer to offload from CPU.
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config MTK_UART_APDMA
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tristate "MediaTek SoCs APDMA support for UART"
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depends on OF && SERIAL_8250_MT6577
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select DMA_ENGINE
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select DMA_VIRTUAL_CHANNELS
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help
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Support for the UART DMA engine found on MediaTek MTK SoCs.
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When SERIAL_8250_MT6577 is enabled, and if you want to use DMA,
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you can enable the config. The DMA engine can only be used
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with MediaTek SoCs.
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@ -1,2 +1,3 @@
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obj-$(CONFIG_MTK_UART_APDMA) += mtk-uart-apdma.o
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obj-$(CONFIG_MTK_HSDMA) += mtk-hsdma.o
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obj-$(CONFIG_MTK_CQDMA) += mtk-cqdma.o
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@ -0,0 +1,666 @@
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// SPDX-License-Identifier: GPL-2.0
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/*
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* MediaTek UART APDMA driver.
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*
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* Copyright (c) 2019 MediaTek Inc.
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* Author: Long Cheng <long.cheng@mediatek.com>
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*/
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#include <linux/clk.h>
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#include <linux/dmaengine.h>
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#include <linux/dma-mapping.h>
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#include <linux/err.h>
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#include <linux/init.h>
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#include <linux/interrupt.h>
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#include <linux/iopoll.h>
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#include <linux/kernel.h>
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#include <linux/list.h>
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#include <linux/module.h>
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#include <linux/of_device.h>
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#include <linux/of_dma.h>
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#include <linux/platform_device.h>
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#include <linux/pm_runtime.h>
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#include <linux/slab.h>
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#include <linux/spinlock.h>
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#include "../virt-dma.h"
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/* The default number of virtual channel */
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#define MTK_UART_APDMA_NR_VCHANS 8
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#define VFF_EN_B BIT(0)
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#define VFF_STOP_B BIT(0)
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#define VFF_FLUSH_B BIT(0)
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#define VFF_4G_EN_B BIT(0)
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/* rx valid size >= vff thre */
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#define VFF_RX_INT_EN_B (BIT(0) | BIT(1))
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/* tx left size >= vff thre */
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#define VFF_TX_INT_EN_B BIT(0)
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#define VFF_WARM_RST_B BIT(0)
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#define VFF_RX_INT_CLR_B (BIT(0) | BIT(1))
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#define VFF_TX_INT_CLR_B 0
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#define VFF_STOP_CLR_B 0
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#define VFF_EN_CLR_B 0
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#define VFF_INT_EN_CLR_B 0
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#define VFF_4G_SUPPORT_CLR_B 0
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/*
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* interrupt trigger level for tx
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* if threshold is n, no polling is required to start tx.
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* otherwise need polling VFF_FLUSH.
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*/
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#define VFF_TX_THRE(n) (n)
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/* interrupt trigger level for rx */
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#define VFF_RX_THRE(n) ((n) * 3 / 4)
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#define VFF_RING_SIZE 0xffff
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/* invert this bit when wrap ring head again */
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#define VFF_RING_WRAP 0x10000
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#define VFF_INT_FLAG 0x00
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#define VFF_INT_EN 0x04
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#define VFF_EN 0x08
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#define VFF_RST 0x0c
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#define VFF_STOP 0x10
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#define VFF_FLUSH 0x14
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#define VFF_ADDR 0x1c
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#define VFF_LEN 0x24
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#define VFF_THRE 0x28
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#define VFF_WPT 0x2c
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#define VFF_RPT 0x30
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/* TX: the buffer size HW can read. RX: the buffer size SW can read. */
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#define VFF_VALID_SIZE 0x3c
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/* TX: the buffer size SW can write. RX: the buffer size HW can write. */
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#define VFF_LEFT_SIZE 0x40
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#define VFF_DEBUG_STATUS 0x50
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#define VFF_4G_SUPPORT 0x54
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struct mtk_uart_apdmadev {
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struct dma_device ddev;
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struct clk *clk;
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bool support_33bits;
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unsigned int dma_requests;
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};
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struct mtk_uart_apdma_desc {
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struct virt_dma_desc vd;
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dma_addr_t addr;
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unsigned int avail_len;
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};
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struct mtk_chan {
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struct virt_dma_chan vc;
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struct dma_slave_config cfg;
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struct mtk_uart_apdma_desc *desc;
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enum dma_transfer_direction dir;
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void __iomem *base;
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unsigned int irq;
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unsigned int rx_status;
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};
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static inline struct mtk_uart_apdmadev *
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to_mtk_uart_apdma_dev(struct dma_device *d)
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{
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return container_of(d, struct mtk_uart_apdmadev, ddev);
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}
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static inline struct mtk_chan *to_mtk_uart_apdma_chan(struct dma_chan *c)
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{
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return container_of(c, struct mtk_chan, vc.chan);
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}
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static inline struct mtk_uart_apdma_desc *to_mtk_uart_apdma_desc
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(struct dma_async_tx_descriptor *t)
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{
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return container_of(t, struct mtk_uart_apdma_desc, vd.tx);
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}
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static void mtk_uart_apdma_write(struct mtk_chan *c,
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unsigned int reg, unsigned int val)
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{
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writel(val, c->base + reg);
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}
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static unsigned int mtk_uart_apdma_read(struct mtk_chan *c, unsigned int reg)
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{
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return readl(c->base + reg);
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}
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static void mtk_uart_apdma_desc_free(struct virt_dma_desc *vd)
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{
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struct dma_chan *chan = vd->tx.chan;
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struct mtk_chan *c = to_mtk_uart_apdma_chan(chan);
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kfree(c->desc);
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}
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static void mtk_uart_apdma_start_tx(struct mtk_chan *c)
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{
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struct mtk_uart_apdmadev *mtkd =
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to_mtk_uart_apdma_dev(c->vc.chan.device);
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struct mtk_uart_apdma_desc *d = c->desc;
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unsigned int wpt, vff_sz;
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vff_sz = c->cfg.dst_port_window_size;
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if (!mtk_uart_apdma_read(c, VFF_LEN)) {
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mtk_uart_apdma_write(c, VFF_ADDR, d->addr);
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mtk_uart_apdma_write(c, VFF_LEN, vff_sz);
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mtk_uart_apdma_write(c, VFF_THRE, VFF_TX_THRE(vff_sz));
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mtk_uart_apdma_write(c, VFF_WPT, 0);
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mtk_uart_apdma_write(c, VFF_INT_FLAG, VFF_TX_INT_CLR_B);
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if (mtkd->support_33bits)
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mtk_uart_apdma_write(c, VFF_4G_SUPPORT, VFF_4G_EN_B);
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}
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mtk_uart_apdma_write(c, VFF_EN, VFF_EN_B);
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if (mtk_uart_apdma_read(c, VFF_EN) != VFF_EN_B)
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dev_err(c->vc.chan.device->dev, "Enable TX fail\n");
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if (!mtk_uart_apdma_read(c, VFF_LEFT_SIZE)) {
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mtk_uart_apdma_write(c, VFF_INT_EN, VFF_TX_INT_EN_B);
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return;
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}
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wpt = mtk_uart_apdma_read(c, VFF_WPT);
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wpt += c->desc->avail_len;
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if ((wpt & VFF_RING_SIZE) == vff_sz)
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wpt = (wpt & VFF_RING_WRAP) ^ VFF_RING_WRAP;
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/* Let DMA start moving data */
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mtk_uart_apdma_write(c, VFF_WPT, wpt);
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/* HW auto set to 0 when left size >= threshold */
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mtk_uart_apdma_write(c, VFF_INT_EN, VFF_TX_INT_EN_B);
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if (!mtk_uart_apdma_read(c, VFF_FLUSH))
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mtk_uart_apdma_write(c, VFF_FLUSH, VFF_FLUSH_B);
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}
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static void mtk_uart_apdma_start_rx(struct mtk_chan *c)
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{
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struct mtk_uart_apdmadev *mtkd =
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to_mtk_uart_apdma_dev(c->vc.chan.device);
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struct mtk_uart_apdma_desc *d = c->desc;
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unsigned int vff_sz;
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vff_sz = c->cfg.src_port_window_size;
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if (!mtk_uart_apdma_read(c, VFF_LEN)) {
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mtk_uart_apdma_write(c, VFF_ADDR, d->addr);
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mtk_uart_apdma_write(c, VFF_LEN, vff_sz);
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mtk_uart_apdma_write(c, VFF_THRE, VFF_RX_THRE(vff_sz));
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mtk_uart_apdma_write(c, VFF_RPT, 0);
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mtk_uart_apdma_write(c, VFF_INT_FLAG, VFF_RX_INT_CLR_B);
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if (mtkd->support_33bits)
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mtk_uart_apdma_write(c, VFF_4G_SUPPORT, VFF_4G_EN_B);
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}
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mtk_uart_apdma_write(c, VFF_INT_EN, VFF_RX_INT_EN_B);
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mtk_uart_apdma_write(c, VFF_EN, VFF_EN_B);
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if (mtk_uart_apdma_read(c, VFF_EN) != VFF_EN_B)
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dev_err(c->vc.chan.device->dev, "Enable RX fail\n");
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}
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static void mtk_uart_apdma_tx_handler(struct mtk_chan *c)
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{
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struct mtk_uart_apdma_desc *d = c->desc;
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mtk_uart_apdma_write(c, VFF_INT_FLAG, VFF_TX_INT_CLR_B);
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mtk_uart_apdma_write(c, VFF_INT_EN, VFF_INT_EN_CLR_B);
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mtk_uart_apdma_write(c, VFF_EN, VFF_EN_CLR_B);
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list_del(&d->vd.node);
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vchan_cookie_complete(&d->vd);
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}
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static void mtk_uart_apdma_rx_handler(struct mtk_chan *c)
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{
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struct mtk_uart_apdma_desc *d = c->desc;
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unsigned int len, wg, rg;
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int cnt;
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mtk_uart_apdma_write(c, VFF_INT_FLAG, VFF_RX_INT_CLR_B);
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if (!mtk_uart_apdma_read(c, VFF_VALID_SIZE))
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return;
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mtk_uart_apdma_write(c, VFF_EN, VFF_EN_CLR_B);
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mtk_uart_apdma_write(c, VFF_INT_EN, VFF_INT_EN_CLR_B);
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len = c->cfg.src_port_window_size;
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rg = mtk_uart_apdma_read(c, VFF_RPT);
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wg = mtk_uart_apdma_read(c, VFF_WPT);
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cnt = (wg & VFF_RING_SIZE) - (rg & VFF_RING_SIZE);
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/*
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* The buffer is ring buffer. If wrap bit different,
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* represents the start of the next cycle for WPT
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*/
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if ((rg ^ wg) & VFF_RING_WRAP)
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cnt += len;
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c->rx_status = d->avail_len - cnt;
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mtk_uart_apdma_write(c, VFF_RPT, wg);
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list_del(&d->vd.node);
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vchan_cookie_complete(&d->vd);
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}
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static irqreturn_t mtk_uart_apdma_irq_handler(int irq, void *dev_id)
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{
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struct dma_chan *chan = (struct dma_chan *)dev_id;
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struct mtk_chan *c = to_mtk_uart_apdma_chan(chan);
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unsigned long flags;
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spin_lock_irqsave(&c->vc.lock, flags);
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if (c->dir == DMA_DEV_TO_MEM)
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mtk_uart_apdma_rx_handler(c);
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else if (c->dir == DMA_MEM_TO_DEV)
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mtk_uart_apdma_tx_handler(c);
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spin_unlock_irqrestore(&c->vc.lock, flags);
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return IRQ_HANDLED;
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}
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static int mtk_uart_apdma_alloc_chan_resources(struct dma_chan *chan)
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{
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struct mtk_uart_apdmadev *mtkd = to_mtk_uart_apdma_dev(chan->device);
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struct mtk_chan *c = to_mtk_uart_apdma_chan(chan);
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unsigned int status;
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int ret;
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ret = pm_runtime_get_sync(mtkd->ddev.dev);
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if (ret < 0) {
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pm_runtime_put_noidle(chan->device->dev);
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return ret;
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}
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mtk_uart_apdma_write(c, VFF_ADDR, 0);
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mtk_uart_apdma_write(c, VFF_THRE, 0);
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mtk_uart_apdma_write(c, VFF_LEN, 0);
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mtk_uart_apdma_write(c, VFF_RST, VFF_WARM_RST_B);
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ret = readx_poll_timeout(readl, c->base + VFF_EN,
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status, !status, 10, 100);
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if (ret)
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return ret;
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ret = request_irq(c->irq, mtk_uart_apdma_irq_handler,
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IRQF_TRIGGER_NONE, KBUILD_MODNAME, chan);
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if (ret < 0) {
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dev_err(chan->device->dev, "Can't request dma IRQ\n");
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return -EINVAL;
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}
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if (mtkd->support_33bits)
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mtk_uart_apdma_write(c, VFF_4G_SUPPORT, VFF_4G_SUPPORT_CLR_B);
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return ret;
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}
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static void mtk_uart_apdma_free_chan_resources(struct dma_chan *chan)
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{
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struct mtk_uart_apdmadev *mtkd = to_mtk_uart_apdma_dev(chan->device);
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struct mtk_chan *c = to_mtk_uart_apdma_chan(chan);
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free_irq(c->irq, chan);
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tasklet_kill(&c->vc.task);
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vchan_free_chan_resources(&c->vc);
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pm_runtime_put_sync(mtkd->ddev.dev);
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}
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static enum dma_status mtk_uart_apdma_tx_status(struct dma_chan *chan,
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dma_cookie_t cookie,
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struct dma_tx_state *txstate)
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{
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struct mtk_chan *c = to_mtk_uart_apdma_chan(chan);
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enum dma_status ret;
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ret = dma_cookie_status(chan, cookie, txstate);
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if (!txstate)
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return ret;
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dma_set_residue(txstate, c->rx_status);
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return ret;
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}
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/*
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* dmaengine_prep_slave_single will call the function. and sglen is 1.
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* 8250 uart using one ring buffer, and deal with one sg.
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*/
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static struct dma_async_tx_descriptor *mtk_uart_apdma_prep_slave_sg
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(struct dma_chan *chan, struct scatterlist *sgl,
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unsigned int sglen, enum dma_transfer_direction dir,
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unsigned long tx_flags, void *context)
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{
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struct mtk_chan *c = to_mtk_uart_apdma_chan(chan);
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struct mtk_uart_apdma_desc *d;
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if (!is_slave_direction(dir) || sglen != 1)
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return NULL;
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/* Now allocate and setup the descriptor */
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d = kzalloc(sizeof(*d), GFP_ATOMIC);
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if (!d)
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return NULL;
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d->avail_len = sg_dma_len(sgl);
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d->addr = sg_dma_address(sgl);
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c->dir = dir;
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return vchan_tx_prep(&c->vc, &d->vd, tx_flags);
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}
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static void mtk_uart_apdma_issue_pending(struct dma_chan *chan)
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{
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struct mtk_chan *c = to_mtk_uart_apdma_chan(chan);
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struct virt_dma_desc *vd;
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unsigned long flags;
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spin_lock_irqsave(&c->vc.lock, flags);
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if (vchan_issue_pending(&c->vc)) {
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vd = vchan_next_desc(&c->vc);
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c->desc = to_mtk_uart_apdma_desc(&vd->tx);
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if (c->dir == DMA_DEV_TO_MEM)
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mtk_uart_apdma_start_rx(c);
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else if (c->dir == DMA_MEM_TO_DEV)
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mtk_uart_apdma_start_tx(c);
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}
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spin_unlock_irqrestore(&c->vc.lock, flags);
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}
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static int mtk_uart_apdma_slave_config(struct dma_chan *chan,
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struct dma_slave_config *config)
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{
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struct mtk_chan *c = to_mtk_uart_apdma_chan(chan);
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memcpy(&c->cfg, config, sizeof(*config));
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return 0;
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}
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static int mtk_uart_apdma_terminate_all(struct dma_chan *chan)
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{
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struct mtk_chan *c = to_mtk_uart_apdma_chan(chan);
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unsigned long flags;
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unsigned int status;
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LIST_HEAD(head);
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int ret;
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mtk_uart_apdma_write(c, VFF_FLUSH, VFF_FLUSH_B);
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|
||||
ret = readx_poll_timeout(readl, c->base + VFF_FLUSH,
|
||||
status, status != VFF_FLUSH_B, 10, 100);
|
||||
if (ret)
|
||||
dev_err(c->vc.chan.device->dev, "flush: fail, status=0x%x\n",
|
||||
mtk_uart_apdma_read(c, VFF_DEBUG_STATUS));
|
||||
|
||||
/*
|
||||
* Stop need 3 steps.
|
||||
* 1. set stop to 1
|
||||
* 2. wait en to 0
|
||||
* 3. set stop as 0
|
||||
*/
|
||||
mtk_uart_apdma_write(c, VFF_STOP, VFF_STOP_B);
|
||||
ret = readx_poll_timeout(readl, c->base + VFF_EN,
|
||||
status, !status, 10, 100);
|
||||
if (ret)
|
||||
dev_err(c->vc.chan.device->dev, "stop: fail, status=0x%x\n",
|
||||
mtk_uart_apdma_read(c, VFF_DEBUG_STATUS));
|
||||
|
||||
mtk_uart_apdma_write(c, VFF_STOP, VFF_STOP_CLR_B);
|
||||
mtk_uart_apdma_write(c, VFF_INT_EN, VFF_INT_EN_CLR_B);
|
||||
|
||||
if (c->dir == DMA_DEV_TO_MEM)
|
||||
mtk_uart_apdma_write(c, VFF_INT_FLAG, VFF_RX_INT_CLR_B);
|
||||
else if (c->dir == DMA_MEM_TO_DEV)
|
||||
mtk_uart_apdma_write(c, VFF_INT_FLAG, VFF_TX_INT_CLR_B);
|
||||
|
||||
synchronize_irq(c->irq);
|
||||
|
||||
spin_lock_irqsave(&c->vc.lock, flags);
|
||||
vchan_get_all_descriptors(&c->vc, &head);
|
||||
vchan_dma_desc_free_list(&c->vc, &head);
|
||||
spin_unlock_irqrestore(&c->vc.lock, flags);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int mtk_uart_apdma_device_pause(struct dma_chan *chan)
|
||||
{
|
||||
struct mtk_chan *c = to_mtk_uart_apdma_chan(chan);
|
||||
unsigned long flags;
|
||||
|
||||
spin_lock_irqsave(&c->vc.lock, flags);
|
||||
|
||||
mtk_uart_apdma_write(c, VFF_EN, VFF_EN_CLR_B);
|
||||
mtk_uart_apdma_write(c, VFF_INT_EN, VFF_INT_EN_CLR_B);
|
||||
|
||||
synchronize_irq(c->irq);
|
||||
|
||||
spin_unlock_irqrestore(&c->vc.lock, flags);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static void mtk_uart_apdma_free(struct mtk_uart_apdmadev *mtkd)
|
||||
{
|
||||
while (!list_empty(&mtkd->ddev.channels)) {
|
||||
struct mtk_chan *c = list_first_entry(&mtkd->ddev.channels,
|
||||
struct mtk_chan, vc.chan.device_node);
|
||||
|
||||
list_del(&c->vc.chan.device_node);
|
||||
tasklet_kill(&c->vc.task);
|
||||
}
|
||||
}
|
||||
|
||||
static const struct of_device_id mtk_uart_apdma_match[] = {
|
||||
{ .compatible = "mediatek,mt6577-uart-dma", },
|
||||
{ /* sentinel */ },
|
||||
};
|
||||
MODULE_DEVICE_TABLE(of, mtk_uart_apdma_match);
|
||||
|
||||
static int mtk_uart_apdma_probe(struct platform_device *pdev)
|
||||
{
|
||||
struct device_node *np = pdev->dev.of_node;
|
||||
struct mtk_uart_apdmadev *mtkd;
|
||||
int bit_mask = 32, rc;
|
||||
struct resource *res;
|
||||
struct mtk_chan *c;
|
||||
unsigned int i;
|
||||
|
||||
mtkd = devm_kzalloc(&pdev->dev, sizeof(*mtkd), GFP_KERNEL);
|
||||
if (!mtkd)
|
||||
return -ENOMEM;
|
||||
|
||||
mtkd->clk = devm_clk_get(&pdev->dev, NULL);
|
||||
if (IS_ERR(mtkd->clk)) {
|
||||
dev_err(&pdev->dev, "No clock specified\n");
|
||||
rc = PTR_ERR(mtkd->clk);
|
||||
return rc;
|
||||
}
|
||||
|
||||
if (of_property_read_bool(np, "mediatek,dma-33bits"))
|
||||
mtkd->support_33bits = true;
|
||||
|
||||
if (mtkd->support_33bits)
|
||||
bit_mask = 33;
|
||||
|
||||
rc = dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(bit_mask));
|
||||
if (rc)
|
||||
return rc;
|
||||
|
||||
dma_cap_set(DMA_SLAVE, mtkd->ddev.cap_mask);
|
||||
mtkd->ddev.device_alloc_chan_resources =
|
||||
mtk_uart_apdma_alloc_chan_resources;
|
||||
mtkd->ddev.device_free_chan_resources =
|
||||
mtk_uart_apdma_free_chan_resources;
|
||||
mtkd->ddev.device_tx_status = mtk_uart_apdma_tx_status;
|
||||
mtkd->ddev.device_issue_pending = mtk_uart_apdma_issue_pending;
|
||||
mtkd->ddev.device_prep_slave_sg = mtk_uart_apdma_prep_slave_sg;
|
||||
mtkd->ddev.device_config = mtk_uart_apdma_slave_config;
|
||||
mtkd->ddev.device_pause = mtk_uart_apdma_device_pause;
|
||||
mtkd->ddev.device_terminate_all = mtk_uart_apdma_terminate_all;
|
||||
mtkd->ddev.src_addr_widths = BIT(DMA_SLAVE_BUSWIDTH_1_BYTE);
|
||||
mtkd->ddev.dst_addr_widths = BIT(DMA_SLAVE_BUSWIDTH_1_BYTE);
|
||||
mtkd->ddev.directions = BIT(DMA_DEV_TO_MEM) | BIT(DMA_MEM_TO_DEV);
|
||||
mtkd->ddev.residue_granularity = DMA_RESIDUE_GRANULARITY_SEGMENT;
|
||||
mtkd->ddev.dev = &pdev->dev;
|
||||
INIT_LIST_HEAD(&mtkd->ddev.channels);
|
||||
|
||||
mtkd->dma_requests = MTK_UART_APDMA_NR_VCHANS;
|
||||
if (of_property_read_u32(np, "dma-requests", &mtkd->dma_requests)) {
|
||||
dev_info(&pdev->dev,
|
||||
"Using %u as missing dma-requests property\n",
|
||||
MTK_UART_APDMA_NR_VCHANS);
|
||||
}
|
||||
|
||||
for (i = 0; i < mtkd->dma_requests; i++) {
|
||||
c = devm_kzalloc(mtkd->ddev.dev, sizeof(*c), GFP_KERNEL);
|
||||
if (!c) {
|
||||
rc = -ENODEV;
|
||||
goto err_no_dma;
|
||||
}
|
||||
|
||||
res = platform_get_resource(pdev, IORESOURCE_MEM, i);
|
||||
if (!res) {
|
||||
rc = -ENODEV;
|
||||
goto err_no_dma;
|
||||
}
|
||||
|
||||
c->base = devm_ioremap_resource(&pdev->dev, res);
|
||||
if (IS_ERR(c->base)) {
|
||||
rc = PTR_ERR(c->base);
|
||||
goto err_no_dma;
|
||||
}
|
||||
c->vc.desc_free = mtk_uart_apdma_desc_free;
|
||||
vchan_init(&c->vc, &mtkd->ddev);
|
||||
|
||||
rc = platform_get_irq(pdev, i);
|
||||
if (rc < 0) {
|
||||
dev_err(&pdev->dev, "failed to get IRQ[%d]\n", i);
|
||||
goto err_no_dma;
|
||||
}
|
||||
c->irq = rc;
|
||||
}
|
||||
|
||||
pm_runtime_enable(&pdev->dev);
|
||||
pm_runtime_set_active(&pdev->dev);
|
||||
|
||||
rc = dma_async_device_register(&mtkd->ddev);
|
||||
if (rc)
|
||||
goto rpm_disable;
|
||||
|
||||
platform_set_drvdata(pdev, mtkd);
|
||||
|
||||
/* Device-tree DMA controller registration */
|
||||
rc = of_dma_controller_register(np, of_dma_xlate_by_chan_id, mtkd);
|
||||
if (rc)
|
||||
goto dma_remove;
|
||||
|
||||
return rc;
|
||||
|
||||
dma_remove:
|
||||
dma_async_device_unregister(&mtkd->ddev);
|
||||
rpm_disable:
|
||||
pm_runtime_disable(&pdev->dev);
|
||||
err_no_dma:
|
||||
mtk_uart_apdma_free(mtkd);
|
||||
return rc;
|
||||
}
|
||||
|
||||
static int mtk_uart_apdma_remove(struct platform_device *pdev)
|
||||
{
|
||||
struct mtk_uart_apdmadev *mtkd = platform_get_drvdata(pdev);
|
||||
|
||||
of_dma_controller_free(pdev->dev.of_node);
|
||||
|
||||
mtk_uart_apdma_free(mtkd);
|
||||
|
||||
dma_async_device_unregister(&mtkd->ddev);
|
||||
|
||||
pm_runtime_disable(&pdev->dev);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
#ifdef CONFIG_PM_SLEEP
|
||||
static int mtk_uart_apdma_suspend(struct device *dev)
|
||||
{
|
||||
struct mtk_uart_apdmadev *mtkd = dev_get_drvdata(dev);
|
||||
|
||||
if (!pm_runtime_suspended(dev))
|
||||
clk_disable_unprepare(mtkd->clk);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int mtk_uart_apdma_resume(struct device *dev)
|
||||
{
|
||||
int ret;
|
||||
struct mtk_uart_apdmadev *mtkd = dev_get_drvdata(dev);
|
||||
|
||||
if (!pm_runtime_suspended(dev)) {
|
||||
ret = clk_prepare_enable(mtkd->clk);
|
||||
if (ret)
|
||||
return ret;
|
||||
}
|
||||
|
||||
return 0;
|
||||
}
|
||||
#endif /* CONFIG_PM_SLEEP */
|
||||
|
||||
#ifdef CONFIG_PM
|
||||
static int mtk_uart_apdma_runtime_suspend(struct device *dev)
|
||||
{
|
||||
struct mtk_uart_apdmadev *mtkd = dev_get_drvdata(dev);
|
||||
|
||||
clk_disable_unprepare(mtkd->clk);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int mtk_uart_apdma_runtime_resume(struct device *dev)
|
||||
{
|
||||
int ret;
|
||||
struct mtk_uart_apdmadev *mtkd = dev_get_drvdata(dev);
|
||||
|
||||
ret = clk_prepare_enable(mtkd->clk);
|
||||
if (ret)
|
||||
return ret;
|
||||
|
||||
return 0;
|
||||
}
|
||||
#endif /* CONFIG_PM */
|
||||
|
||||
static const struct dev_pm_ops mtk_uart_apdma_pm_ops = {
|
||||
SET_SYSTEM_SLEEP_PM_OPS(mtk_uart_apdma_suspend, mtk_uart_apdma_resume)
|
||||
SET_RUNTIME_PM_OPS(mtk_uart_apdma_runtime_suspend,
|
||||
mtk_uart_apdma_runtime_resume, NULL)
|
||||
};
|
||||
|
||||
static struct platform_driver mtk_uart_apdma_driver = {
|
||||
.probe = mtk_uart_apdma_probe,
|
||||
.remove = mtk_uart_apdma_remove,
|
||||
.driver = {
|
||||
.name = KBUILD_MODNAME,
|
||||
.pm = &mtk_uart_apdma_pm_ops,
|
||||
.of_match_table = of_match_ptr(mtk_uart_apdma_match),
|
||||
},
|
||||
};
|
||||
|
||||
module_platform_driver(mtk_uart_apdma_driver);
|
||||
|
||||
MODULE_DESCRIPTION("MediaTek UART APDMA Controller Driver");
|
||||
MODULE_AUTHOR("Long Cheng <long.cheng@mediatek.com>");
|
||||
MODULE_LICENSE("GPL v2");
|
||||
Loading…
Reference in New Issue