drm/radeon: halt engines before disabling MC (cayman/TN)
It's better to halt the engines before we disable the MC. Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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@ -1405,13 +1405,6 @@ static void cayman_gpu_soft_reset(struct radeon_device *rdev, u32 reset_mask)
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dev_info(rdev->dev, " VM_CONTEXT1_PROTECTION_FAULT_STATUS 0x%08X\n",
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dev_info(rdev->dev, " VM_CONTEXT1_PROTECTION_FAULT_STATUS 0x%08X\n",
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RREG32(0x14DC));
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RREG32(0x14DC));
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r600_set_bios_scratch_engine_hung(rdev, true);
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evergreen_mc_stop(rdev, &save);
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if (evergreen_mc_wait_for_idle(rdev)) {
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dev_warn(rdev->dev, "Wait for MC idle timedout !\n");
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}
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/* Disable CP parsing/prefetching */
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/* Disable CP parsing/prefetching */
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WREG32(CP_ME_CNTL, CP_ME_HALT | CP_PFP_HALT);
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WREG32(CP_ME_CNTL, CP_ME_HALT | CP_PFP_HALT);
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@ -1429,6 +1422,13 @@ static void cayman_gpu_soft_reset(struct radeon_device *rdev, u32 reset_mask)
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WREG32(DMA_RB_CNTL + DMA1_REGISTER_OFFSET, tmp);
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WREG32(DMA_RB_CNTL + DMA1_REGISTER_OFFSET, tmp);
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}
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}
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udelay(50);
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evergreen_mc_stop(rdev, &save);
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if (evergreen_mc_wait_for_idle(rdev)) {
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dev_warn(rdev->dev, "Wait for MC idle timedout !\n");
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}
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if (reset_mask & (RADEON_RESET_GFX | RADEON_RESET_COMPUTE)) {
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if (reset_mask & (RADEON_RESET_GFX | RADEON_RESET_COMPUTE)) {
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grbm_soft_reset = SOFT_RESET_CB |
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grbm_soft_reset = SOFT_RESET_CB |
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SOFT_RESET_DB |
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SOFT_RESET_DB |
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