- plan atomic check oops fix

- fix CVBS init when HDMI is configured by bootloader
 - fix CVBS VDAC disable
 -----BEGIN PGP SIGNATURE-----
 Version: GnuPG v1
 
 iQIcBAABAgAGBQJYbNg7AAoJEHfc29rIyEnRGVgP/REA7QN/AWgsFj4RElq0+m/F
 K4vYZK1AqvbSOy6wgXCxjQdYwkZiCB2FM77PNkgR30Cvnz11uIyRw7FTiyENY7RG
 e1kEoqC9/Vfl+BfAHb6pzhwaa403hiYLzb6/AAVyS+IGh6RbcP0J9OclqPST5lQW
 1QbqYXJmMU4aekQ65+1gkmIX0gb2EMNvKvtLrkcSweR9nJ2A4VYJL6VsTO51OKkg
 aBwZx2sRtf4xIwQcbdZB2Bb6TTVceLQLjUb1gZ06kJ5CjUchzMGg2wrRue7+XUg9
 bPhNovvq6/6OsyTAPCnBt2pIHWGMqjlUe+SLiLJJB2jtvh9r2fnKgxEMjGLeKAGx
 ltFJmz3MNT6v9jYdhMJJqIsizbM9sJUTN1q6ZqdhJThW//KP+DRycRH9V7xrTN9K
 vcBPMBmWSEc1WjBqucCcN08WU83eLaOpkOODl4CI5REoGwkCrq6HjH0jjWVk4B95
 +brDQgzTLs7KM2Jn2bhq9MRYu06HyWfrZVtLYA1dptl6N+oxlBhVy48MxDvjCq8B
 x/Wf2ZLQGX2lOUwWb1n9jmoyduaSbekCrQEnJThx0NWwqE22SdDL+k6UbW2U3bDF
 Oe3YAl8+ZLTmxKkwyk66aq2OGvlkwaXpgBzKQQykaSr87WsQjWuAcaRP/wmglZPl
 KCcTiDInskjtrJIzXF4u
 =mbs3
 -----END PGP SIGNATURE-----

Merge tag 'meson-drm-fixes-for-4.10' of git://people.freedesktop.org/~narmstrong/linux into drm-fixes

- plan atomic check oops fix
- fix CVBS init when HDMI is configured by bootloader
- fix CVBS VDAC disable

* tag 'meson-drm-fixes-for-4.10' of git://people.freedesktop.org/~narmstrong/linux:
  drm/meson: Fix CVBS VDAC disable
  drm/meson: Fix CVBS initialization when HDMI is configured by bootloader
  drm/meson: Fix plane atomic check when no crtc for the plane

drivers/gpu/drm/meson/meson_plane.c

@@ -51,6 +51,9 @@ static int meson_plane_atomic_check(struct drm_plane *plane,
 	struct drm_crtc_state *crtc_state;
 	struct drm_rect clip = { 0, };
 
+	if (!state->crtc)
+		return 0;
+
 	crtc_state = drm_atomic_get_crtc_state(state->state, state->crtc);
 	if (IS_ERR(crtc_state))
 		return PTR_ERR(crtc_state);

drivers/gpu/drm/meson/meson_venc.c

@@ -38,6 +38,11 @@
  * - TV Panel encoding via ENCT
  */
 
+/* HHI Registers */
+#define HHI_VDAC_CNTL0		0x2F4 /* 0xbd offset in data sheet */
+#define HHI_VDAC_CNTL1		0x2F8 /* 0xbe offset in data sheet */
+#define HHI_HDMI_PHY_CNTL0	0x3a0 /* 0xe8 offset in data sheet */
+
 struct meson_cvbs_enci_mode meson_cvbs_enci_pal = {
 	.mode_tag = MESON_VENC_MODE_CVBS_PAL,
 	.hso_begin = 3,
@@ -242,6 +247,20 @@ void meson_venc_disable_vsync(struct meson_drm *priv)
 
 void meson_venc_init(struct meson_drm *priv)
 {
+	/* Disable CVBS VDAC */
+	regmap_write(priv->hhi, HHI_VDAC_CNTL0, 0);
+	regmap_write(priv->hhi, HHI_VDAC_CNTL1, 8);
+
+	/* Power Down Dacs */
+	writel_relaxed(0xff, priv->io_base + _REG(VENC_VDAC_SETTING));
+
+	/* Disable HDMI PHY */
+	regmap_write(priv->hhi, HHI_HDMI_PHY_CNTL0, 0);
+
+	/* Disable HDMI */
+	writel_bits_relaxed(0x3, 0,
+			    priv->io_base + _REG(VPU_HDMI_SETTING));
+
 	/* Disable all encoders */
 	writel_relaxed(0, priv->io_base + _REG(ENCI_VIDEO_EN));
 	writel_relaxed(0, priv->io_base + _REG(ENCP_VIDEO_EN));

drivers/gpu/drm/meson/meson_venc_cvbs.c

@@ -167,7 +167,7 @@ static void meson_venc_cvbs_encoder_disable(struct drm_encoder *encoder)
 
 	/* Disable CVBS VDAC */
 	regmap_write(priv->hhi, HHI_VDAC_CNTL0, 0);
-	regmap_write(priv->hhi, HHI_VDAC_CNTL1, 0);
+	regmap_write(priv->hhi, HHI_VDAC_CNTL1, 8);
 }
 
 static void meson_venc_cvbs_encoder_enable(struct drm_encoder *encoder)