KVM: arm64: Get rid of the AArch32 register mapping code
The only use of the register mapping code was for the sake of the LR mapping, which we trivially solved in a previous patch. Get rid of the whole thing now. Signed-off-by: Marc Zyngier <maz@kernel.org>
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@ -33,8 +33,6 @@ enum exception_type {
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except_type_serror = 0x180,
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};
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unsigned long *vcpu_reg32(const struct kvm_vcpu *vcpu, u8 reg_num);
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bool kvm_condition_valid32(const struct kvm_vcpu *vcpu);
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void kvm_skip_instr32(struct kvm_vcpu *vcpu);
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@ -13,7 +13,7 @@ obj-$(CONFIG_KVM) += hyp/
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kvm-y := $(KVM)/kvm_main.o $(KVM)/coalesced_mmio.o $(KVM)/eventfd.o \
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$(KVM)/vfio.o $(KVM)/irqchip.o \
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arm.o mmu.o mmio.o psci.o perf.o hypercalls.o pvtime.o \
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inject_fault.o regmap.o va_layout.o handle_exit.o \
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inject_fault.o va_layout.o handle_exit.o \
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guest.o debug.o reset.o sys_regs.o \
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vgic-sys-reg-v3.o fpsimd.o pmu.o \
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arch_timer.o \
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@ -252,10 +252,32 @@ static int set_core_reg(struct kvm_vcpu *vcpu, const struct kvm_one_reg *reg)
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memcpy(addr, valp, KVM_REG_SIZE(reg->id));
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if (*vcpu_cpsr(vcpu) & PSR_MODE32_BIT) {
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int i;
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int i, nr_reg;
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for (i = 0; i < 16; i++)
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*vcpu_reg32(vcpu, i) = (u32)*vcpu_reg32(vcpu, i);
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switch (*vcpu_cpsr(vcpu)) {
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/*
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* Either we are dealing with user mode, and only the
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* first 15 registers (+ PC) must be narrowed to 32bit.
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* AArch32 r0-r14 conveniently map to AArch64 x0-x14.
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*/
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case PSR_AA32_MODE_USR:
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case PSR_AA32_MODE_SYS:
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nr_reg = 15;
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break;
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/*
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* Otherwide, this is a priviledged mode, and *all* the
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* registers must be narrowed to 32bit.
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*/
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default:
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nr_reg = 31;
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break;
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}
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for (i = 0; i < nr_reg; i++)
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vcpu_set_reg(vcpu, i, (u32)vcpu_get_reg(vcpu, i));
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*vcpu_pc(vcpu) = (u32)*vcpu_pc(vcpu);
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}
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out:
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return err;
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@ -1,128 +0,0 @@
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// SPDX-License-Identifier: GPL-2.0-only
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/*
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* Copyright (C) 2012,2013 - ARM Ltd
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* Author: Marc Zyngier <marc.zyngier@arm.com>
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*
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* Derived from arch/arm/kvm/emulate.c:
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* Copyright (C) 2012 - Virtual Open Systems and Columbia University
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* Author: Christoffer Dall <c.dall@virtualopensystems.com>
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*/
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#include <linux/mm.h>
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#include <linux/kvm_host.h>
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#include <asm/kvm_emulate.h>
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#include <asm/ptrace.h>
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#define VCPU_NR_MODES 6
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#define REG_OFFSET(_reg) \
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(offsetof(struct user_pt_regs, _reg) / sizeof(unsigned long))
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#define USR_REG_OFFSET(R) REG_OFFSET(compat_usr(R))
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static const unsigned long vcpu_reg_offsets[VCPU_NR_MODES][16] = {
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/* USR Registers */
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{
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USR_REG_OFFSET(0), USR_REG_OFFSET(1), USR_REG_OFFSET(2),
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USR_REG_OFFSET(3), USR_REG_OFFSET(4), USR_REG_OFFSET(5),
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USR_REG_OFFSET(6), USR_REG_OFFSET(7), USR_REG_OFFSET(8),
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USR_REG_OFFSET(9), USR_REG_OFFSET(10), USR_REG_OFFSET(11),
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USR_REG_OFFSET(12), USR_REG_OFFSET(13), USR_REG_OFFSET(14),
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REG_OFFSET(pc)
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},
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/* FIQ Registers */
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{
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USR_REG_OFFSET(0), USR_REG_OFFSET(1), USR_REG_OFFSET(2),
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USR_REG_OFFSET(3), USR_REG_OFFSET(4), USR_REG_OFFSET(5),
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USR_REG_OFFSET(6), USR_REG_OFFSET(7),
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REG_OFFSET(compat_r8_fiq), /* r8 */
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REG_OFFSET(compat_r9_fiq), /* r9 */
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REG_OFFSET(compat_r10_fiq), /* r10 */
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REG_OFFSET(compat_r11_fiq), /* r11 */
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REG_OFFSET(compat_r12_fiq), /* r12 */
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REG_OFFSET(compat_sp_fiq), /* r13 */
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REG_OFFSET(compat_lr_fiq), /* r14 */
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REG_OFFSET(pc)
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},
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/* IRQ Registers */
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{
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USR_REG_OFFSET(0), USR_REG_OFFSET(1), USR_REG_OFFSET(2),
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USR_REG_OFFSET(3), USR_REG_OFFSET(4), USR_REG_OFFSET(5),
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USR_REG_OFFSET(6), USR_REG_OFFSET(7), USR_REG_OFFSET(8),
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USR_REG_OFFSET(9), USR_REG_OFFSET(10), USR_REG_OFFSET(11),
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USR_REG_OFFSET(12),
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REG_OFFSET(compat_sp_irq), /* r13 */
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REG_OFFSET(compat_lr_irq), /* r14 */
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REG_OFFSET(pc)
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},
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/* SVC Registers */
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{
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USR_REG_OFFSET(0), USR_REG_OFFSET(1), USR_REG_OFFSET(2),
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USR_REG_OFFSET(3), USR_REG_OFFSET(4), USR_REG_OFFSET(5),
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USR_REG_OFFSET(6), USR_REG_OFFSET(7), USR_REG_OFFSET(8),
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USR_REG_OFFSET(9), USR_REG_OFFSET(10), USR_REG_OFFSET(11),
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USR_REG_OFFSET(12),
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REG_OFFSET(compat_sp_svc), /* r13 */
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REG_OFFSET(compat_lr_svc), /* r14 */
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REG_OFFSET(pc)
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},
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/* ABT Registers */
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{
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USR_REG_OFFSET(0), USR_REG_OFFSET(1), USR_REG_OFFSET(2),
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USR_REG_OFFSET(3), USR_REG_OFFSET(4), USR_REG_OFFSET(5),
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USR_REG_OFFSET(6), USR_REG_OFFSET(7), USR_REG_OFFSET(8),
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USR_REG_OFFSET(9), USR_REG_OFFSET(10), USR_REG_OFFSET(11),
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USR_REG_OFFSET(12),
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REG_OFFSET(compat_sp_abt), /* r13 */
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REG_OFFSET(compat_lr_abt), /* r14 */
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REG_OFFSET(pc)
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},
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/* UND Registers */
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{
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USR_REG_OFFSET(0), USR_REG_OFFSET(1), USR_REG_OFFSET(2),
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USR_REG_OFFSET(3), USR_REG_OFFSET(4), USR_REG_OFFSET(5),
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USR_REG_OFFSET(6), USR_REG_OFFSET(7), USR_REG_OFFSET(8),
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USR_REG_OFFSET(9), USR_REG_OFFSET(10), USR_REG_OFFSET(11),
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USR_REG_OFFSET(12),
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REG_OFFSET(compat_sp_und), /* r13 */
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REG_OFFSET(compat_lr_und), /* r14 */
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REG_OFFSET(pc)
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},
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};
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/*
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* Return a pointer to the register number valid in the current mode of
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* the virtual CPU.
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*/
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unsigned long *vcpu_reg32(const struct kvm_vcpu *vcpu, u8 reg_num)
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{
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unsigned long *reg_array = (unsigned long *)&vcpu->arch.ctxt.regs;
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unsigned long mode = *vcpu_cpsr(vcpu) & PSR_AA32_MODE_MASK;
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switch (mode) {
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case PSR_AA32_MODE_USR ... PSR_AA32_MODE_SVC:
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mode &= ~PSR_MODE32_BIT; /* 0 ... 3 */
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break;
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case PSR_AA32_MODE_ABT:
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mode = 4;
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break;
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case PSR_AA32_MODE_UND:
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mode = 5;
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break;
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case PSR_AA32_MODE_SYS:
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mode = 0; /* SYS maps to USR */
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break;
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default:
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BUG();
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}
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return reg_array + vcpu_reg_offsets[mode][reg_num];
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}
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