spi: add support for Amlogic A1 SPI Flash Controller
This is a driver for the Amlogic SPI flash controller support on A113L SoC. Signed-off-by: Martin Kurbanov <mmkurbanov@sberdevices.ru> Reviewed-by: Neil Armstrong <neil.armstrong@linaro.org> Link: https://lore.kernel.org/r/20230403183217.13280-3-mmkurbanov@sberdevices.ru Signed-off-by: Mark Brown <broonie@kernel.org>
This commit is contained in:
Martin Kurbanov
Mark Brown
parent
d040fe8f9f
commit
909fac05b9
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@ -79,6 +79,13 @@ config SPI_ALTERA_DFL
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Altera SPI master controller. The SPI master is connected
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to a SPI slave to Avalon bridge in a Intel MAX BMC.
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config SPI_AMLOGIC_SPIFC_A1
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tristate "Amlogic A1 SPIFC controller"
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depends on ARCH_MESON || COMPILE_TEST
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help
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This enables master mode support for the SPIFC (SPI flash
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controller) available in Amlogic A1 (A113L SoC).
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config SPI_AR934X
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tristate "Qualcomm Atheros AR934X/QCA95XX SPI controller driver"
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depends on ATH79 || COMPILE_TEST
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@ -17,6 +17,7 @@ obj-$(CONFIG_SPI_LOOPBACK_TEST) += spi-loopback-test.o
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obj-$(CONFIG_SPI_ALTERA) += spi-altera-platform.o
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obj-$(CONFIG_SPI_ALTERA_CORE) += spi-altera-core.o
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obj-$(CONFIG_SPI_ALTERA_DFL) += spi-altera-dfl.o
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obj-$(CONFIG_SPI_AMLOGIC_SPIFC_A1) += spi-amlogic-spifc-a1.o
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obj-$(CONFIG_SPI_AR934X) += spi-ar934x.o
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obj-$(CONFIG_SPI_ARMADA_3700) += spi-armada-3700.o
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obj-$(CONFIG_SPI_ASPEED_SMC) += spi-aspeed-smc.o
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@ -0,0 +1,456 @@
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// SPDX-License-Identifier: GPL-2.0
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/*
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* Driver for Amlogic A1 SPI flash controller (SPIFC)
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*
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* Copyright (c) 2023, SberDevices. All Rights Reserved.
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*
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* Author: Martin Kurbanov <mmkurbanov@sberdevices.ru>
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*/
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#include <linux/bitfield.h>
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#include <linux/clk.h>
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#include <linux/device.h>
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#include <linux/io.h>
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#include <linux/iopoll.h>
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#include <linux/kernel.h>
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#include <linux/module.h>
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#include <linux/of.h>
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#include <linux/platform_device.h>
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#include <linux/pm_runtime.h>
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#include <linux/spi/spi.h>
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#include <linux/spi/spi-mem.h>
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#include <linux/types.h>
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#define SPIFC_A1_AHB_CTRL_REG 0x0
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#define SPIFC_A1_AHB_BUS_EN BIT(31)
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#define SPIFC_A1_USER_CTRL0_REG 0x200
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#define SPIFC_A1_USER_REQUEST_ENABLE BIT(31)
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#define SPIFC_A1_USER_REQUEST_FINISH BIT(30)
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#define SPIFC_A1_USER_DATA_UPDATED BIT(0)
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#define SPIFC_A1_USER_CTRL1_REG 0x204
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#define SPIFC_A1_USER_CMD_ENABLE BIT(30)
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#define SPIFC_A1_USER_CMD_MODE GENMASK(29, 28)
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#define SPIFC_A1_USER_CMD_CODE GENMASK(27, 20)
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#define SPIFC_A1_USER_ADDR_ENABLE BIT(19)
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#define SPIFC_A1_USER_ADDR_MODE GENMASK(18, 17)
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#define SPIFC_A1_USER_ADDR_BYTES GENMASK(16, 15)
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#define SPIFC_A1_USER_DOUT_ENABLE BIT(14)
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#define SPIFC_A1_USER_DOUT_MODE GENMASK(11, 10)
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#define SPIFC_A1_USER_DOUT_BYTES GENMASK(9, 0)
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#define SPIFC_A1_USER_CTRL2_REG 0x208
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#define SPIFC_A1_USER_DUMMY_ENABLE BIT(31)
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#define SPIFC_A1_USER_DUMMY_MODE GENMASK(30, 29)
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#define SPIFC_A1_USER_DUMMY_CLK_SYCLES GENMASK(28, 23)
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#define SPIFC_A1_USER_CTRL3_REG 0x20c
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#define SPIFC_A1_USER_DIN_ENABLE BIT(31)
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#define SPIFC_A1_USER_DIN_MODE GENMASK(28, 27)
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#define SPIFC_A1_USER_DIN_BYTES GENMASK(25, 16)
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#define SPIFC_A1_USER_ADDR_REG 0x210
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#define SPIFC_A1_AHB_REQ_CTRL_REG 0x214
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#define SPIFC_A1_AHB_REQ_ENABLE BIT(31)
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#define SPIFC_A1_ACTIMING0_REG (0x0088 << 2)
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#define SPIFC_A1_TSLCH GENMASK(31, 30)
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#define SPIFC_A1_TCLSH GENMASK(29, 28)
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#define SPIFC_A1_TSHWL GENMASK(20, 16)
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#define SPIFC_A1_TSHSL2 GENMASK(15, 12)
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#define SPIFC_A1_TSHSL1 GENMASK(11, 8)
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#define SPIFC_A1_TWHSL GENMASK(7, 0)
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#define SPIFC_A1_DBUF_CTRL_REG 0x240
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#define SPIFC_A1_DBUF_DIR BIT(31)
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#define SPIFC_A1_DBUF_AUTO_UPDATE_ADDR BIT(30)
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#define SPIFC_A1_DBUF_ADDR GENMASK(7, 0)
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#define SPIFC_A1_DBUF_DATA_REG 0x244
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#define SPIFC_A1_USER_DBUF_ADDR_REG 0x248
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#define SPIFC_A1_BUFFER_SIZE 512
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#define SPIFC_A1_MAX_HZ 200000000
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#define SPIFC_A1_MIN_HZ 1000000
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#define SPIFC_A1_USER_CMD(op) ( \
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SPIFC_A1_USER_CMD_ENABLE | \
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FIELD_PREP(SPIFC_A1_USER_CMD_CODE, (op)->cmd.opcode) | \
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FIELD_PREP(SPIFC_A1_USER_CMD_MODE, ilog2((op)->cmd.buswidth)))
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#define SPIFC_A1_USER_ADDR(op) ( \
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SPIFC_A1_USER_ADDR_ENABLE | \
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FIELD_PREP(SPIFC_A1_USER_ADDR_MODE, ilog2((op)->addr.buswidth)) | \
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FIELD_PREP(SPIFC_A1_USER_ADDR_BYTES, (op)->addr.nbytes - 1))
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#define SPIFC_A1_USER_DUMMY(op) ( \
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SPIFC_A1_USER_DUMMY_ENABLE | \
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FIELD_PREP(SPIFC_A1_USER_DUMMY_MODE, ilog2((op)->dummy.buswidth)) | \
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FIELD_PREP(SPIFC_A1_USER_DUMMY_CLK_SYCLES, (op)->dummy.nbytes << 3))
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#define SPIFC_A1_TSLCH_VAL FIELD_PREP(SPIFC_A1_TSLCH, 1)
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#define SPIFC_A1_TCLSH_VAL FIELD_PREP(SPIFC_A1_TCLSH, 1)
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#define SPIFC_A1_TSHWL_VAL FIELD_PREP(SPIFC_A1_TSHWL, 7)
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#define SPIFC_A1_TSHSL2_VAL FIELD_PREP(SPIFC_A1_TSHSL2, 7)
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#define SPIFC_A1_TSHSL1_VAL FIELD_PREP(SPIFC_A1_TSHSL1, 7)
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#define SPIFC_A1_TWHSL_VAL FIELD_PREP(SPIFC_A1_TWHSL, 2)
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#define SPIFC_A1_ACTIMING0_VAL (SPIFC_A1_TSLCH_VAL | SPIFC_A1_TCLSH_VAL | \
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SPIFC_A1_TSHWL_VAL | SPIFC_A1_TSHSL2_VAL | \
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SPIFC_A1_TSHSL1_VAL | SPIFC_A1_TWHSL_VAL)
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struct amlogic_spifc_a1 {
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struct spi_controller *ctrl;
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struct clk *clk;
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struct device *dev;
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void __iomem *base;
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};
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static int amlogic_spifc_a1_request(struct amlogic_spifc_a1 *spifc, bool read)
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{
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u32 mask = SPIFC_A1_USER_REQUEST_FINISH |
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(read ? SPIFC_A1_USER_DATA_UPDATED : 0);
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u32 val;
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writel(SPIFC_A1_USER_REQUEST_ENABLE,
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spifc->base + SPIFC_A1_USER_CTRL0_REG);
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return readl_poll_timeout(spifc->base + SPIFC_A1_USER_CTRL0_REG,
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val, (val & mask) == mask, 0,
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200 * USEC_PER_MSEC);
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}
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static void amlogic_spifc_a1_drain_buffer(struct amlogic_spifc_a1 *spifc,
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char *buf, u32 len)
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{
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u32 data;
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const u32 count = len / sizeof(data);
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const u32 pad = len % sizeof(data);
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writel(SPIFC_A1_DBUF_AUTO_UPDATE_ADDR,
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spifc->base + SPIFC_A1_DBUF_CTRL_REG);
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ioread32_rep(spifc->base + SPIFC_A1_DBUF_DATA_REG, buf, count);
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if (pad) {
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data = readl(spifc->base + SPIFC_A1_DBUF_DATA_REG);
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memcpy(buf + len - pad, &data, pad);
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}
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}
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static void amlogic_spifc_a1_fill_buffer(struct amlogic_spifc_a1 *spifc,
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const char *buf, u32 len)
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{
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u32 data;
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const u32 count = len / sizeof(data);
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const u32 pad = len % sizeof(data);
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writel(SPIFC_A1_DBUF_DIR | SPIFC_A1_DBUF_AUTO_UPDATE_ADDR,
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spifc->base + SPIFC_A1_DBUF_CTRL_REG);
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iowrite32_rep(spifc->base + SPIFC_A1_DBUF_DATA_REG, buf, count);
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if (pad) {
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memcpy(&data, buf + len - pad, pad);
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writel(data, spifc->base + SPIFC_A1_DBUF_DATA_REG);
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}
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}
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static void amlogic_spifc_a1_user_init(struct amlogic_spifc_a1 *spifc)
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{
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writel(0, spifc->base + SPIFC_A1_USER_CTRL0_REG);
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writel(0, spifc->base + SPIFC_A1_USER_CTRL1_REG);
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writel(0, spifc->base + SPIFC_A1_USER_CTRL2_REG);
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writel(0, spifc->base + SPIFC_A1_USER_CTRL3_REG);
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}
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static void amlogic_spifc_a1_set_cmd(struct amlogic_spifc_a1 *spifc,
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u32 cmd_cfg)
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{
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u32 val;
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val = readl(spifc->base + SPIFC_A1_USER_CTRL1_REG);
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val &= ~(SPIFC_A1_USER_CMD_MODE | SPIFC_A1_USER_CMD_CODE);
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val |= cmd_cfg;
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writel(val, spifc->base + SPIFC_A1_USER_CTRL1_REG);
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}
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static void amlogic_spifc_a1_set_addr(struct amlogic_spifc_a1 *spifc, u32 addr,
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u32 addr_cfg)
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{
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u32 val;
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writel(addr, spifc->base + SPIFC_A1_USER_ADDR_REG);
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val = readl(spifc->base + SPIFC_A1_USER_CTRL1_REG);
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val &= ~(SPIFC_A1_USER_ADDR_MODE | SPIFC_A1_USER_ADDR_BYTES);
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val |= addr_cfg;
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writel(val, spifc->base + SPIFC_A1_USER_CTRL1_REG);
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}
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static void amlogic_spifc_a1_set_dummy(struct amlogic_spifc_a1 *spifc,
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u32 dummy_cfg)
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{
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u32 val = readl(spifc->base + SPIFC_A1_USER_CTRL2_REG);
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val &= ~(SPIFC_A1_USER_DUMMY_MODE | SPIFC_A1_USER_DUMMY_CLK_SYCLES);
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val |= dummy_cfg;
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writel(val, spifc->base + SPIFC_A1_USER_CTRL2_REG);
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}
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static int amlogic_spifc_a1_read(struct amlogic_spifc_a1 *spifc, void *buf,
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u32 size, u32 mode)
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{
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u32 val = readl(spifc->base + SPIFC_A1_USER_CTRL3_REG);
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int ret;
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val &= ~(SPIFC_A1_USER_DIN_MODE | SPIFC_A1_USER_DIN_BYTES);
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val |= SPIFC_A1_USER_DIN_ENABLE;
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val |= FIELD_PREP(SPIFC_A1_USER_DIN_MODE, mode);
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val |= FIELD_PREP(SPIFC_A1_USER_DIN_BYTES, size);
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writel(val, spifc->base + SPIFC_A1_USER_CTRL3_REG);
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ret = amlogic_spifc_a1_request(spifc, true);
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if (!ret)
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amlogic_spifc_a1_drain_buffer(spifc, buf, size);
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return ret;
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}
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static int amlogic_spifc_a1_write(struct amlogic_spifc_a1 *spifc,
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const void *buf, u32 size, u32 mode)
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{
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u32 val;
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amlogic_spifc_a1_fill_buffer(spifc, buf, size);
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val = readl(spifc->base + SPIFC_A1_USER_CTRL1_REG);
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val &= ~(SPIFC_A1_USER_DOUT_MODE | SPIFC_A1_USER_DOUT_BYTES);
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val |= FIELD_PREP(SPIFC_A1_USER_DOUT_MODE, mode);
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val |= FIELD_PREP(SPIFC_A1_USER_DOUT_BYTES, size);
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val |= SPIFC_A1_USER_DOUT_ENABLE;
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writel(val, spifc->base + SPIFC_A1_USER_CTRL1_REG);
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return amlogic_spifc_a1_request(spifc, false);
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}
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static int amlogic_spifc_a1_exec_op(struct spi_mem *mem,
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const struct spi_mem_op *op)
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{
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struct amlogic_spifc_a1 *spifc =
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spi_controller_get_devdata(mem->spi->controller);
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size_t off, nbytes = op->data.nbytes;
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u32 cmd_cfg, addr_cfg, dummy_cfg, dmode;
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int ret;
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amlogic_spifc_a1_user_init(spifc);
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cmd_cfg = SPIFC_A1_USER_CMD(op);
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amlogic_spifc_a1_set_cmd(spifc, cmd_cfg);
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if (op->addr.nbytes) {
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addr_cfg = SPIFC_A1_USER_ADDR(op);
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amlogic_spifc_a1_set_addr(spifc, op->addr.val, addr_cfg);
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}
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if (op->dummy.nbytes) {
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dummy_cfg = SPIFC_A1_USER_DUMMY(op);
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amlogic_spifc_a1_set_dummy(spifc, dummy_cfg);
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}
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if (!op->data.nbytes)
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return amlogic_spifc_a1_request(spifc, false);
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dmode = ilog2(op->data.buswidth);
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off = 0;
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do {
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size_t block_size = min_t(size_t, nbytes, SPIFC_A1_BUFFER_SIZE);
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amlogic_spifc_a1_set_cmd(spifc, cmd_cfg);
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if (op->addr.nbytes)
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amlogic_spifc_a1_set_addr(spifc, op->addr.val + off,
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addr_cfg);
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if (op->dummy.nbytes)
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amlogic_spifc_a1_set_dummy(spifc, dummy_cfg);
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writel(0, spifc->base + SPIFC_A1_USER_DBUF_ADDR_REG);
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if (op->data.dir == SPI_MEM_DATA_IN)
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ret = amlogic_spifc_a1_read(spifc,
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op->data.buf.in + off,
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block_size, dmode);
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else
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ret = amlogic_spifc_a1_write(spifc,
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op->data.buf.out + off,
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block_size, dmode);
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nbytes -= block_size;
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off += block_size;
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} while (nbytes != 0 && !ret);
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return ret;
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}
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static void amlogic_spifc_a1_hw_init(struct amlogic_spifc_a1 *spifc)
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{
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u32 regv;
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regv = readl(spifc->base + SPIFC_A1_AHB_REQ_CTRL_REG);
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regv &= ~(SPIFC_A1_AHB_REQ_ENABLE);
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writel(regv, spifc->base + SPIFC_A1_AHB_REQ_CTRL_REG);
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regv = readl(spifc->base + SPIFC_A1_AHB_CTRL_REG);
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regv &= ~(SPIFC_A1_AHB_BUS_EN);
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writel(regv, spifc->base + SPIFC_A1_AHB_CTRL_REG);
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writel(SPIFC_A1_ACTIMING0_VAL, spifc->base + SPIFC_A1_ACTIMING0_REG);
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writel(0, spifc->base + SPIFC_A1_USER_DBUF_ADDR_REG);
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}
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static const struct spi_controller_mem_ops amlogic_spifc_a1_mem_ops = {
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.exec_op = amlogic_spifc_a1_exec_op,
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};
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static int amlogic_spifc_a1_probe(struct platform_device *pdev)
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{
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struct spi_controller *ctrl;
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struct amlogic_spifc_a1 *spifc;
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int ret;
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ctrl = devm_spi_alloc_master(&pdev->dev, sizeof(*spifc));
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if (!ctrl)
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return -ENOMEM;
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spifc = spi_controller_get_devdata(ctrl);
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platform_set_drvdata(pdev, spifc);
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spifc->dev = &pdev->dev;
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spifc->ctrl = ctrl;
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spifc->base = devm_platform_ioremap_resource(pdev, 0);
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if (IS_ERR(spifc->base))
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return PTR_ERR(spifc->base);
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spifc->clk = devm_clk_get_enabled(spifc->dev, NULL);
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if (IS_ERR(spifc->clk))
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return dev_err_probe(spifc->dev, PTR_ERR(spifc->clk),
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"unable to get clock\n");
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amlogic_spifc_a1_hw_init(spifc);
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pm_runtime_set_autosuspend_delay(spifc->dev, 500);
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pm_runtime_use_autosuspend(spifc->dev);
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||||
devm_pm_runtime_enable(spifc->dev);
|
||||
|
||||
ctrl->num_chipselect = 1;
|
||||
ctrl->dev.of_node = pdev->dev.of_node;
|
||||
ctrl->bits_per_word_mask = SPI_BPW_MASK(8);
|
||||
ctrl->auto_runtime_pm = true;
|
||||
ctrl->mem_ops = &amlogic_spifc_a1_mem_ops;
|
||||
ctrl->min_speed_hz = SPIFC_A1_MIN_HZ;
|
||||
ctrl->max_speed_hz = SPIFC_A1_MAX_HZ;
|
||||
ctrl->mode_bits = (SPI_RX_DUAL | SPI_TX_DUAL |
|
||||
SPI_RX_QUAD | SPI_TX_QUAD);
|
||||
|
||||
ret = devm_spi_register_controller(spifc->dev, ctrl);
|
||||
if (ret)
|
||||
return dev_err_probe(spifc->dev, ret,
|
||||
"failed to register spi controller\n");
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
#ifdef CONFIG_PM_SLEEP
|
||||
static int amlogic_spifc_a1_suspend(struct device *dev)
|
||||
{
|
||||
struct amlogic_spifc_a1 *spifc = dev_get_drvdata(dev);
|
||||
int ret;
|
||||
|
||||
ret = spi_controller_suspend(spifc->ctrl);
|
||||
if (ret)
|
||||
return ret;
|
||||
|
||||
if (!pm_runtime_suspended(dev))
|
||||
clk_disable_unprepare(spifc->clk);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int amlogic_spifc_a1_resume(struct device *dev)
|
||||
{
|
||||
struct amlogic_spifc_a1 *spifc = dev_get_drvdata(dev);
|
||||
int ret = 0;
|
||||
|
||||
if (!pm_runtime_suspended(dev)) {
|
||||
ret = clk_prepare_enable(spifc->clk);
|
||||
if (ret)
|
||||
return ret;
|
||||
}
|
||||
|
||||
amlogic_spifc_a1_hw_init(spifc);
|
||||
|
||||
ret = spi_controller_resume(spifc->ctrl);
|
||||
if (ret)
|
||||
clk_disable_unprepare(spifc->clk);
|
||||
|
||||
return ret;
|
||||
}
|
||||
#endif /* CONFIG_PM_SLEEP */
|
||||
|
||||
#ifdef CONFIG_PM
|
||||
static int amlogic_spifc_a1_runtime_suspend(struct device *dev)
|
||||
{
|
||||
struct amlogic_spifc_a1 *spifc = dev_get_drvdata(dev);
|
||||
|
||||
clk_disable_unprepare(spifc->clk);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int amlogic_spifc_a1_runtime_resume(struct device *dev)
|
||||
{
|
||||
struct amlogic_spifc_a1 *spifc = dev_get_drvdata(dev);
|
||||
int ret;
|
||||
|
||||
ret = clk_prepare_enable(spifc->clk);
|
||||
if (!ret)
|
||||
amlogic_spifc_a1_hw_init(spifc);
|
||||
|
||||
return ret;
|
||||
}
|
||||
#endif /* CONFIG_PM */
|
||||
|
||||
static const struct dev_pm_ops amlogic_spifc_a1_pm_ops = {
|
||||
SET_SYSTEM_SLEEP_PM_OPS(amlogic_spifc_a1_suspend,
|
||||
amlogic_spifc_a1_resume)
|
||||
SET_RUNTIME_PM_OPS(amlogic_spifc_a1_runtime_suspend,
|
||||
amlogic_spifc_a1_runtime_resume,
|
||||
NULL)
|
||||
};
|
||||
|
||||
#ifdef CONFIG_OF
|
||||
static const struct of_device_id amlogic_spifc_a1_dt_match[] = {
|
||||
{ .compatible = "amlogic,a1-spifc", },
|
||||
{ },
|
||||
};
|
||||
MODULE_DEVICE_TABLE(of, amlogic_spifc_a1_dt_match);
|
||||
#endif /* CONFIG_OF */
|
||||
|
||||
static struct platform_driver amlogic_spifc_a1_driver = {
|
||||
.probe = amlogic_spifc_a1_probe,
|
||||
.driver = {
|
||||
.name = "amlogic-spifc-a1",
|
||||
.of_match_table = of_match_ptr(amlogic_spifc_a1_dt_match),
|
||||
.pm = &amlogic_spifc_a1_pm_ops,
|
||||
},
|
||||
};
|
||||
module_platform_driver(amlogic_spifc_a1_driver);
|
||||
|
||||
MODULE_AUTHOR("Martin Kurbanov <mmkurbanov@sberdevices.ru>");
|
||||
MODULE_DESCRIPTION("Amlogic A1 SPIFC driver");
|
||||
MODULE_LICENSE("GPL");
|
||||
Loading…
Reference in New Issue