habanalabs: halt the engines before hard-reset
The driver must halt the engines before doing hard-reset, otherwise the device can go into undefined state. There is a place where the driver didn't do that and this patch fixes it. Reviewed-by: Tomer Tayar <ttayar@habana.ai> Signed-off-by: Oded Gabbay <oded.gabbay@gmail.com>
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@ -1189,6 +1189,7 @@ int hl_device_init(struct hl_device *hdev, struct class *hclass)
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if (hdev->asic_funcs->get_hw_state(hdev) == HL_DEVICE_HW_STATE_DIRTY) {
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dev_info(hdev->dev,
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"H/W state is dirty, must reset before initializing\n");
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hdev->asic_funcs->halt_engines(hdev, true);
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hdev->asic_funcs->hw_fini(hdev, true);
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}
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@ -895,6 +895,11 @@ void goya_init_dma_qmans(struct hl_device *hdev)
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*/
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static void goya_disable_external_queues(struct hl_device *hdev)
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{
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struct goya_device *goya = hdev->asic_specific;
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if (!(goya->hw_cap_initialized & HW_CAP_DMA))
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return;
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WREG32(mmDMA_QM_0_GLBL_CFG0, 0);
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WREG32(mmDMA_QM_1_GLBL_CFG0, 0);
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WREG32(mmDMA_QM_2_GLBL_CFG0, 0);
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@ -956,6 +961,11 @@ static int goya_stop_external_queues(struct hl_device *hdev)
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{
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int rc, retval = 0;
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struct goya_device *goya = hdev->asic_specific;
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if (!(goya->hw_cap_initialized & HW_CAP_DMA))
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return retval;
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rc = goya_stop_queue(hdev,
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mmDMA_QM_0_GLBL_CFG1,
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mmDMA_QM_0_CP_STS,
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@ -1744,9 +1754,18 @@ void goya_init_tpc_qmans(struct hl_device *hdev)
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*/
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static void goya_disable_internal_queues(struct hl_device *hdev)
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{
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struct goya_device *goya = hdev->asic_specific;
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if (!(goya->hw_cap_initialized & HW_CAP_MME))
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goto disable_tpc;
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WREG32(mmMME_QM_GLBL_CFG0, 0);
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WREG32(mmMME_CMDQ_GLBL_CFG0, 0);
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disable_tpc:
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if (!(goya->hw_cap_initialized & HW_CAP_TPC))
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return;
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WREG32(mmTPC0_QM_GLBL_CFG0, 0);
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WREG32(mmTPC0_CMDQ_GLBL_CFG0, 0);
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@ -1782,8 +1801,12 @@ static void goya_disable_internal_queues(struct hl_device *hdev)
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*/
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static int goya_stop_internal_queues(struct hl_device *hdev)
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{
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struct goya_device *goya = hdev->asic_specific;
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int rc, retval = 0;
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if (!(goya->hw_cap_initialized & HW_CAP_MME))
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goto stop_tpc;
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/*
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* Each queue (QMAN) is a separate H/W logic. That means that each
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* QMAN can be stopped independently and failure to stop one does NOT
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@ -1810,6 +1833,10 @@ static int goya_stop_internal_queues(struct hl_device *hdev)
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retval = -EIO;
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}
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stop_tpc:
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if (!(goya->hw_cap_initialized & HW_CAP_TPC))
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return retval;
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rc = goya_stop_queue(hdev,
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mmTPC0_QM_GLBL_CFG1,
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mmTPC0_QM_CP_STS,
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@ -1975,6 +2002,11 @@ static int goya_stop_internal_queues(struct hl_device *hdev)
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static void goya_dma_stall(struct hl_device *hdev)
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{
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struct goya_device *goya = hdev->asic_specific;
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if (!(goya->hw_cap_initialized & HW_CAP_DMA))
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return;
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WREG32(mmDMA_QM_0_GLBL_CFG1, 1 << DMA_QM_0_GLBL_CFG1_DMA_STOP_SHIFT);
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WREG32(mmDMA_QM_1_GLBL_CFG1, 1 << DMA_QM_1_GLBL_CFG1_DMA_STOP_SHIFT);
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WREG32(mmDMA_QM_2_GLBL_CFG1, 1 << DMA_QM_2_GLBL_CFG1_DMA_STOP_SHIFT);
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@ -1984,6 +2016,11 @@ static void goya_dma_stall(struct hl_device *hdev)
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static void goya_tpc_stall(struct hl_device *hdev)
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{
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struct goya_device *goya = hdev->asic_specific;
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if (!(goya->hw_cap_initialized & HW_CAP_TPC))
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return;
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WREG32(mmTPC0_CFG_TPC_STALL, 1 << TPC0_CFG_TPC_STALL_V_SHIFT);
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WREG32(mmTPC1_CFG_TPC_STALL, 1 << TPC1_CFG_TPC_STALL_V_SHIFT);
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WREG32(mmTPC2_CFG_TPC_STALL, 1 << TPC2_CFG_TPC_STALL_V_SHIFT);
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@ -1996,6 +2033,11 @@ static void goya_tpc_stall(struct hl_device *hdev)
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static void goya_mme_stall(struct hl_device *hdev)
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{
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struct goya_device *goya = hdev->asic_specific;
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if (!(goya->hw_cap_initialized & HW_CAP_MME))
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return;
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WREG32(mmMME_STALL, 0xFFFFFFFF);
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}
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