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ARM: dts: Fix some mux and divider clocks to get dm814x-evm booting 

Although we have hp t410 booting, I noticed that dm814x-evm does not boot
after I got one. This is because we don't have the clocks yet configured
properly. Let's start configuring proper clocks starting with the system
timers and clocks that work with existing mux and divider clock drivers.

Note that the oscillator speed register is different from am335x, dm814x
has only one bit that shows the BTMODE[6] at CONTROL_STATUS[21].

Also note that this only gets the system timers working with the defined
clocks. The PLL clocks are still missing and and the devices may or may
not work depending on what the bootloader has enabled.

Signed-off-by: Tony Lindgren <tony@atomide.com>
This commit is contained in:
Tony Lindgren 2015-12-03 12:02:31 -08:00
parent 4e34df0cba
commit 9079446dbc
1 changed files with 81 additions and 32 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

113
arch/arm/boot/dts/dm814x-clocks.dtsi
View File

@ -4,18 +4,41 @@
* published by the Free Software Foundation.
*/
&scm_clocks {
tclkin_ck: tclkin_ck {
&pllss_clocks {
timer1_fck: timer1_fck {
#clock-cells = <0>;
compatible = "fixed-clock";
clock-frequency = <32768>;
compatible = "ti,mux-clock";
clocks = <&sysclk18_ck &aud_clkin0_ck &aud_clkin1_ck
&aud_clkin2_ck &devosc_ck &auxosc_ck &tclkin_ck>;
ti,bit-shift = <3>;
reg = <0x2e0>;
};
timer2_fck: timer2_fck {
#clock-cells = <0>;
compatible = "ti,mux-clock";
clocks = <&sysclk18_ck &aud_clkin0_ck &aud_clkin1_ck
&aud_clkin2_ck &devosc_ck &auxosc_ck &tclkin_ck>;
ti,bit-shift = <6>;
reg = <0x2e0>;
};
sysclk18_ck: sysclk18_ck {
#clock-cells = <0>;
compatible = "ti,mux-clock";
clocks = <&rtcosc_ck>, <&rtcdivider_ck>;
ti,bit-shift = <0>;
reg = <0x02f0>;
};
};
&scm_clocks {
devosc_ck: devosc_ck {
#clock-cells = <0>;
compatible = "fixed-clock";
clock-frequency = <20000000>;
compatible = "ti,mux-clock";
clocks = <&virt_20000000_ck>, <&virt_19200000_ck>;
ti,bit-shift = <21>;
reg = <0x0040>;
};
/* Optional auxosc, 20 - 30 MHz range, assume 27 MHz by default */
@ -25,6 +48,32 @@
clock-frequency = <27000000>;
};
/* Optional 32768Hz crystal or clock on RTCOSC pins */
rtcosc_ck: rtcosc_ck {
#clock-cells = <0>;
compatible = "fixed-clock";
clock-frequency = <32768>;
};
/* Optional external clock on TCLKIN pin, set rate in baord dts file */
tclkin_ck: tclkin_ck {
#clock-cells = <0>;
compatible = "fixed-clock";
clock-frequency = <0>;
};
virt_20000000_ck: virt_20000000_ck {
#clock-cells = <0>;
compatible = "fixed-clock";
clock-frequency = <20000000>;
};
virt_19200000_ck: virt_19200000_ck {
#clock-cells = <0>;
compatible = "fixed-clock";
clock-frequency = <19200000>;
};
mpu_ck: mpu_ck {
#clock-cells = <0>;
compatible = "fixed-clock";
@ -49,12 +98,6 @@
clock-frequency = <48000000>;
};
sysclk18_ck: sysclk18_ck {
#clock-cells = <0>;
compatible = "fixed-clock";
clock-frequency = <32768>;
};
cpsw_125mhz_gclk: cpsw_125mhz_gclk {
#clock-cells = <0>;
compatible = "fixed-clock";
@ -69,7 +112,31 @@
};
&pllss_clocks {
&prcm_clocks {
osc_src_ck: osc_src_ck {
#clock-cells = <0>;
compatible = "fixed-factor-clock";
clocks = <&devosc_ck>;
clock-mult = <1>;
clock-div = <1>;
};
mpu_clksrc_ck: mpu_clksrc_ck {
#clock-cells = <0>;
compatible = "ti,mux-clock";
clocks = <&devosc_ck>, <&rtcdivider_ck>;
ti,bit-shift = <0>;
reg = <0x0040>;
};
/* Fixed divider clock 0.0016384 * devosc */
rtcdivider_ck: rtcdivider_ck {
#clock-cells = <0>;
compatible = "fixed-factor-clock";
clocks = <&devosc_ck>;
clock-mult = <128>;
clock-div = <78125>;
};
aud_clkin0_ck: aud_clkin0_ck {
#clock-cells = <0>;
@ -88,22 +155,4 @@
compatible = "fixed-clock";
clock-frequency = <20000000>;
};
timer1_mux_ck: timer1_mux_ck {
#clock-cells = <0>;
compatible = "ti,mux-clock";
clocks = <&sysclk18_ck &aud_clkin0_ck &aud_clkin1_ck
&aud_clkin2_ck &devosc_ck &auxosc_ck &tclkin_ck>;
ti,bit-shift = <3>;
reg = <0x2e0>;
};
timer2_mux_ck: timer2_mux_ck {
#clock-cells = <0>;
compatible = "ti,mux-clock";
clocks = <&sysclk18_ck &aud_clkin0_ck &aud_clkin1_ck
&aud_clkin2_ck &devosc_ck &auxosc_ck &tclkin_ck>;
ti,bit-shift = <6>;
reg = <0x2e0>;
};
};