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ARM: OMAP2+: PRCM: store also physical addresses for instances 

In some cases the physical address info is needed, so store this
under the existing cm*_base, prm_base and prcm_mpu_base variables.
These are converted now to structs that contain both virtual and
physical address base for the instance.

Signed-off-by: Tero Kristo <t-kristo@ti.com>
Signed-off-by: Tony Lindgren <tony@atomide.com>
This commit is contained in:
Tero Kristo 2017-05-31 18:00:00 +03:00 committed by Tony Lindgren
parent 24d8d498a8
commit 9012933671
16 changed files with 82 additions and 56 deletions
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7
arch/arm/mach-omap2/cm.h
View File

@ -24,8 +24,11 @@
# ifndef __ASSEMBLER__ # ifndef __ASSEMBLER__
#include <linux/clk/ti.h> #include <linux/clk/ti.h>
extern void __iomem *cm_base;
extern void __iomem *cm2_base; #include "prcm-common.h"
extern struct omap_domain_base cm_base;
extern struct omap_domain_base cm2_base;
extern void omap2_set_globals_cm(void __iomem *cm, void __iomem *cm2); extern void omap2_set_globals_cm(void __iomem *cm, void __iomem *cm2);
# endif # endif

4
arch/arm/mach-omap2/cm2xxx_3xxx.h
View File

@ -52,12 +52,12 @@
static inline u32 omap2_cm_read_mod_reg(s16 module, u16 idx) static inline u32 omap2_cm_read_mod_reg(s16 module, u16 idx)
{ {
return readl_relaxed(cm_base + module + idx); return readl_relaxed(cm_base.va + module + idx);
} }
static inline void omap2_cm_write_mod_reg(u32 val, s16 module, u16 idx) static inline void omap2_cm_write_mod_reg(u32 val, s16 module, u16 idx)
{ {
writel_relaxed(val, cm_base + module + idx); writel_relaxed(val, cm_base.va + module + idx);
} }
/* Read-modify-write a register in a CM module. Caller must lock */ /* Read-modify-write a register in a CM module. Caller must lock */

4
arch/arm/mach-omap2/cm33xx.c
View File

@ -50,13 +50,13 @@
/* Read a register in a CM instance */ /* Read a register in a CM instance */
static inline u32 am33xx_cm_read_reg(u16 inst, u16 idx) static inline u32 am33xx_cm_read_reg(u16 inst, u16 idx)
{ {
return readl_relaxed(cm_base + inst + idx); return readl_relaxed(cm_base.va + inst + idx);
} }
/* Write into a register in a CM */ /* Write into a register in a CM */
static inline void am33xx_cm_write_reg(u32 val, u16 inst, u16 idx) static inline void am33xx_cm_write_reg(u32 val, u16 inst, u16 idx)
{ {
writel_relaxed(val, cm_base + inst + idx); writel_relaxed(val, cm_base.va + inst + idx);
} }
/* Read-modify-write a register in CM */ /* Read-modify-write a register in CM */

3
arch/arm/mach-omap2/cm3xxx.c
View File

@ -669,7 +669,8 @@ static struct cm_ll_data omap3xxx_cm_ll_data = {
int __init omap3xxx_cm_init(const struct omap_prcm_init_data *data) int __init omap3xxx_cm_init(const struct omap_prcm_init_data *data)
{ {
omap2_clk_legacy_provider_init(TI_CLKM_CM, cm_base + OMAP3430_IVA2_MOD); omap2_clk_legacy_provider_init(TI_CLKM_CM, cm_base.va +
OMAP3430_IVA2_MOD);
return cm_register(&omap3xxx_cm_ll_data); return cm_register(&omap3xxx_cm_ll_data);
} }

31
arch/arm/mach-omap2/cm_common.c
View File

@ -32,10 +32,10 @@ static struct cm_ll_data null_cm_ll_data;
static struct cm_ll_data *cm_ll_data = &null_cm_ll_data; static struct cm_ll_data *cm_ll_data = &null_cm_ll_data;
/* cm_base: base virtual address of the CM IP block */ /* cm_base: base virtual address of the CM IP block */
void __iomem *cm_base; struct omap_domain_base cm_base;
/* cm2_base: base virtual address of the CM2 IP block (OMAP44xx only) */ /* cm2_base: base virtual address of the CM2 IP block (OMAP44xx only) */
void __iomem *cm2_base; struct omap_domain_base cm2_base;
#define CM_NO_CLOCKS 0x1 #define CM_NO_CLOCKS 0x1
#define CM_SINGLE_INSTANCE 0x2 #define CM_SINGLE_INSTANCE 0x2
@ -49,8 +49,8 @@ void __iomem *cm2_base;
*/ */
void __init omap2_set_globals_cm(void __iomem *cm, void __iomem *cm2) void __init omap2_set_globals_cm(void __iomem *cm, void __iomem *cm2)
{ {
cm_base = cm; cm_base.va = cm;
cm2_base = cm2; cm2_base.va = cm2;
} }
/** /**
@ -315,27 +315,34 @@ int __init omap2_cm_base_init(void)
struct device_node *np; struct device_node *np;
const struct of_device_id *match; const struct of_device_id *match;
struct omap_prcm_init_data *data; struct omap_prcm_init_data *data;
void __iomem *mem; struct resource res;
int ret;
struct omap_domain_base *mem = NULL;
for_each_matching_node_and_match(np, omap_cm_dt_match_table, &match) { for_each_matching_node_and_match(np, omap_cm_dt_match_table, &match) {
data = (struct omap_prcm_init_data *)match->data; data = (struct omap_prcm_init_data *)match->data;
mem = of_iomap(np, 0); ret = of_address_to_resource(np, 0, &res);
if (!mem) if (ret)
return -ENOMEM; return ret;
if (data->index == TI_CLKM_CM) if (data->index == TI_CLKM_CM)
cm_base = mem + data->offset; mem = &cm_base;
if (data->index == TI_CLKM_CM2) if (data->index == TI_CLKM_CM2)
cm2_base = mem + data->offset; mem = &cm2_base;
data->mem = mem; data->mem = ioremap(res.start, resource_size(&res));
if (mem) {
mem->pa = res.start + data->offset;
mem->va = data->mem + data->offset;
}
data->np = np; data->np = np;
if (data->init && (data->flags & CM_SINGLE_INSTANCE || if (data->init && (data->flags & CM_SINGLE_INSTANCE ||
(cm_base && cm2_base))) (cm_base.va && cm2_base.va)))
data->init(data); data->init(data);
} }

19
arch/arm/mach-omap2/cminst44xx.c
View File

@ -55,7 +55,7 @@
#define CLKCTRL_IDLEST_INTERFACE_IDLE 0x2 #define CLKCTRL_IDLEST_INTERFACE_IDLE 0x2
#define CLKCTRL_IDLEST_DISABLED 0x3 #define CLKCTRL_IDLEST_DISABLED 0x3
static void __iomem *_cm_bases[OMAP4_MAX_PRCM_PARTITIONS]; static struct omap_domain_base _cm_bases[OMAP4_MAX_PRCM_PARTITIONS];
/** /**
* omap_cm_base_init - Populates the cm partitions * omap_cm_base_init - Populates the cm partitions
@ -65,10 +65,11 @@ static void __iomem *_cm_bases[OMAP4_MAX_PRCM_PARTITIONS];
*/ */
static void omap_cm_base_init(void) static void omap_cm_base_init(void)
{ {
_cm_bases[OMAP4430_PRM_PARTITION] = prm_base; memcpy(&_cm_bases[OMAP4430_PRM_PARTITION], &prm_base, sizeof(prm_base));
_cm_bases[OMAP4430_CM1_PARTITION] = cm_base; memcpy(&_cm_bases[OMAP4430_CM1_PARTITION], &cm_base, sizeof(cm_base));
_cm_bases[OMAP4430_CM2_PARTITION] = cm2_base; memcpy(&_cm_bases[OMAP4430_CM2_PARTITION], &cm2_base, sizeof(cm2_base));
_cm_bases[OMAP4430_PRCM_MPU_PARTITION] = prcm_mpu_base; memcpy(&_cm_bases[OMAP4430_PRCM_MPU_PARTITION], &prcm_mpu_base,
sizeof(prcm_mpu_base));
} }
/* Private functions */ /* Private functions */
@ -116,8 +117,8 @@ static u32 omap4_cminst_read_inst_reg(u8 part, u16 inst, u16 idx)
{ {
BUG_ON(part >= OMAP4_MAX_PRCM_PARTITIONS || BUG_ON(part >= OMAP4_MAX_PRCM_PARTITIONS ||
part == OMAP4430_INVALID_PRCM_PARTITION || part == OMAP4430_INVALID_PRCM_PARTITION ||
!_cm_bases[part]); !_cm_bases[part].va);
return readl_relaxed(_cm_bases[part] + inst + idx); return readl_relaxed(_cm_bases[part].va + inst + idx);
} }
/* Write into a register in a CM instance */ /* Write into a register in a CM instance */
@ -125,8 +126,8 @@ static void omap4_cminst_write_inst_reg(u32 val, u8 part, u16 inst, u16 idx)
{ {
BUG_ON(part >= OMAP4_MAX_PRCM_PARTITIONS || BUG_ON(part >= OMAP4_MAX_PRCM_PARTITIONS ||
part == OMAP4430_INVALID_PRCM_PARTITION || part == OMAP4430_INVALID_PRCM_PARTITION ||
!_cm_bases[part]); !_cm_bases[part].va);
writel_relaxed(val, _cm_bases[part] + inst + idx); writel_relaxed(val, _cm_bases[part].va + inst + idx);
} }
/* Read-modify-write a register in CM1. Caller must lock */ /* Read-modify-write a register in CM1. Caller must lock */

7
arch/arm/mach-omap2/prcm-common.h
View File

@ -526,10 +526,16 @@ struct omap_prcm_irq_setup {
.priority = _priority \ .priority = _priority \
} }
struct omap_domain_base {
u32 pa;
void __iomem *va;
};
/** /**
* struct omap_prcm_init_data - PRCM driver init data * struct omap_prcm_init_data - PRCM driver init data
* @index: clock memory mapping index to be used * @index: clock memory mapping index to be used
* @mem: IO mem pointer for this module * @mem: IO mem pointer for this module
* @phys: IO mem physical base address for this module
* @offset: module base address offset from the IO base * @offset: module base address offset from the IO base
* @flags: PRCM module init flags * @flags: PRCM module init flags
* @device_inst_offset: device instance offset within the module address space * @device_inst_offset: device instance offset within the module address space
@ -539,6 +545,7 @@ struct omap_prcm_irq_setup {
struct omap_prcm_init_data { struct omap_prcm_init_data {
int index; int index;
void __iomem *mem; void __iomem *mem;
u32 phys;
s16 offset; s16 offset;
u16 flags; u16 flags;
s32 device_inst_offset; s32 device_inst_offset;

4
arch/arm/mach-omap2/prcm_mpu44xx.c
View File

@ -24,7 +24,7 @@
* prcm_mpu_base: the virtual address of the start of the PRCM_MPU IP * prcm_mpu_base: the virtual address of the start of the PRCM_MPU IP
* block registers * block registers
*/ */
void __iomem *prcm_mpu_base; struct omap_domain_base prcm_mpu_base;
/* PRCM_MPU low-level functions */ /* PRCM_MPU low-level functions */
@ -58,5 +58,5 @@ u32 omap4_prcm_mpu_rmw_inst_reg_bits(u32 mask, u32 bits, s16 inst, s16 reg)
*/ */
void __init omap2_set_globals_prcm_mpu(void __iomem *prcm_mpu) void __init omap2_set_globals_prcm_mpu(void __iomem *prcm_mpu)
{ {
prcm_mpu_base = prcm_mpu; prcm_mpu_base.va = prcm_mpu;
} }

4
arch/arm/mach-omap2/prcm_mpu_44xx_54xx.h
View File

@ -24,7 +24,9 @@
#define __ARCH_ARM_MACH_OMAP2_PRCM_MPU_44XX_54XX_H #define __ARCH_ARM_MACH_OMAP2_PRCM_MPU_44XX_54XX_H
#ifndef __ASSEMBLER__ #ifndef __ASSEMBLER__
extern void __iomem *prcm_mpu_base; #include "prcm-common.h"
extern struct omap_domain_base prcm_mpu_base;
extern u32 omap4_prcm_mpu_read_inst_reg(s16 inst, u16 idx); extern u32 omap4_prcm_mpu_read_inst_reg(s16 inst, u16 idx);
extern void omap4_prcm_mpu_write_inst_reg(u32 val, s16 inst, u16 idx); extern void omap4_prcm_mpu_write_inst_reg(u32 val, s16 inst, u16 idx);

2
arch/arm/mach-omap2/prm.h
View File

@ -16,7 +16,7 @@
#include "prcm-common.h" #include "prcm-common.h"
# ifndef __ASSEMBLER__ # ifndef __ASSEMBLER__
extern void __iomem *prm_base; extern struct omap_domain_base prm_base;
extern u16 prm_features; extern u16 prm_features;
extern void omap2_set_globals_prm(void __iomem *prm); extern void omap2_set_globals_prm(void __iomem *prm);
int omap_prcm_init(void); int omap_prcm_init(void);

4
arch/arm/mach-omap2/prm2xxx_3xxx.h
View File

@ -55,12 +55,12 @@
/* Power/reset management domain register get/set */ /* Power/reset management domain register get/set */
static inline u32 omap2_prm_read_mod_reg(s16 module, u16 idx) static inline u32 omap2_prm_read_mod_reg(s16 module, u16 idx)
{ {
return readl_relaxed(prm_base + module + idx); return readl_relaxed(prm_base.va + module + idx);
} }
static inline void omap2_prm_write_mod_reg(u32 val, s16 module, u16 idx) static inline void omap2_prm_write_mod_reg(u32 val, s16 module, u16 idx)
{ {
writel_relaxed(val, prm_base + module + idx); writel_relaxed(val, prm_base.va + module + idx);
} }
/* Read-modify-write a register in a PRM module. Caller must lock */ /* Read-modify-write a register in a PRM module. Caller must lock */

4
arch/arm/mach-omap2/prm33xx.c
View File

@ -30,13 +30,13 @@
/* Read a register in a PRM instance */ /* Read a register in a PRM instance */
static u32 am33xx_prm_read_reg(s16 inst, u16 idx) static u32 am33xx_prm_read_reg(s16 inst, u16 idx)
{ {
return readl_relaxed(prm_base + inst + idx); return readl_relaxed(prm_base.va + inst + idx);
} }
/* Write into a register in a PRM instance */ /* Write into a register in a PRM instance */
static void am33xx_prm_write_reg(u32 val, s16 inst, u16 idx) static void am33xx_prm_write_reg(u32 val, s16 inst, u16 idx)
{ {
writel_relaxed(val, prm_base + inst + idx); writel_relaxed(val, prm_base.va + inst + idx);
} }
/* Read-modify-write a register in PRM. Caller must lock */ /* Read-modify-write a register in PRM. Caller must lock */

2
arch/arm/mach-omap2/prm3xxx.c
View File

@ -676,7 +676,7 @@ static struct prm_ll_data omap3xxx_prm_ll_data = {
int __init omap3xxx_prm_init(const struct omap_prcm_init_data *data) int __init omap3xxx_prm_init(const struct omap_prcm_init_data *data)
{ {
omap2_clk_legacy_provider_init(TI_CLKM_PRM, omap2_clk_legacy_provider_init(TI_CLKM_PRM,
prm_base + OMAP3430_IVA2_MOD); prm_base.va + OMAP3430_IVA2_MOD);
if (omap3_has_io_wakeup()) if (omap3_has_io_wakeup())
prm_features |= PRM_HAS_IO_WAKEUP; prm_features |= PRM_HAS_IO_WAKEUP;

4
arch/arm/mach-omap2/prm44xx.c
View File

@ -91,13 +91,13 @@ static struct prm_reset_src_map omap44xx_prm_reset_src_map[] = {
/* Read a register in a CM/PRM instance in the PRM module */ /* Read a register in a CM/PRM instance in the PRM module */
static u32 omap4_prm_read_inst_reg(s16 inst, u16 reg) static u32 omap4_prm_read_inst_reg(s16 inst, u16 reg)
{ {
return readl_relaxed(prm_base + inst + reg); return readl_relaxed(prm_base.va + inst + reg);
} }
/* Write into a register in a CM/PRM instance in the PRM module */ /* Write into a register in a CM/PRM instance in the PRM module */
static void omap4_prm_write_inst_reg(u32 val, s16 inst, u16 reg) static void omap4_prm_write_inst_reg(u32 val, s16 inst, u16 reg)
{ {
writel_relaxed(val, prm_base + inst + reg); writel_relaxed(val, prm_base.va + inst + reg);
} }
/* Read-modify-write a register in a PRM module. Caller must lock */ /* Read-modify-write a register in a PRM module. Caller must lock */

23
arch/arm/mach-omap2/prm_common.c
View File

@ -66,7 +66,7 @@ static struct irq_chip_generic **prcm_irq_chips;
static struct omap_prcm_irq_setup *prcm_irq_setup; static struct omap_prcm_irq_setup *prcm_irq_setup;
/* prm_base: base virtual address of the PRM IP block */ /* prm_base: base virtual address of the PRM IP block */
void __iomem *prm_base; struct omap_domain_base prm_base;
u16 prm_features; u16 prm_features;
@ -325,7 +325,7 @@ int omap_prcm_register_chain_handler(struct omap_prcm_irq_setup *irq_setup)
for (i = 0; i < irq_setup->nr_regs; i++) { for (i = 0; i < irq_setup->nr_regs; i++) {
gc = irq_alloc_generic_chip("PRCM", 1, gc = irq_alloc_generic_chip("PRCM", 1,
irq_setup->base_irq + i * 32, prm_base, irq_setup->base_irq + i * 32, prm_base.va,
handle_level_irq); handle_level_irq);
if (!gc) { if (!gc) {
@ -364,7 +364,7 @@ err:
*/ */
void __init omap2_set_globals_prm(void __iomem *prm) void __init omap2_set_globals_prm(void __iomem *prm)
{ {
prm_base = prm; prm_base.va = prm;
} }
/** /**
@ -755,19 +755,22 @@ int __init omap2_prm_base_init(void)
struct device_node *np; struct device_node *np;
const struct of_device_id *match; const struct of_device_id *match;
struct omap_prcm_init_data *data; struct omap_prcm_init_data *data;
void __iomem *mem; struct resource res;
int ret;
for_each_matching_node_and_match(np, omap_prcm_dt_match_table, &match) { for_each_matching_node_and_match(np, omap_prcm_dt_match_table, &match) {
data = (struct omap_prcm_init_data *)match->data; data = (struct omap_prcm_init_data *)match->data;
mem = of_iomap(np, 0); ret = of_address_to_resource(np, 0, &res);
if (!mem) if (ret)
return -ENOMEM; return ret;
if (data->index == TI_CLKM_PRM) data->mem = ioremap(res.start, resource_size(&res));
prm_base = mem + data->offset;
data->mem = mem; if (data->index == TI_CLKM_PRM) {
prm_base.va = data->mem + data->offset;
prm_base.pa = res.start + data->offset;
}
data->np = np; data->np = np;

16
arch/arm/mach-omap2/prminst44xx.c
View File

@ -29,7 +29,7 @@
#include "prcm_mpu44xx.h" #include "prcm_mpu44xx.h"
#include "soc.h" #include "soc.h"
static void __iomem *_prm_bases[OMAP4_MAX_PRCM_PARTITIONS]; static struct omap_domain_base _prm_bases[OMAP4_MAX_PRCM_PARTITIONS];
static s32 prm_dev_inst = PRM_INSTANCE_UNKNOWN; static s32 prm_dev_inst = PRM_INSTANCE_UNKNOWN;
@ -41,8 +41,10 @@ static s32 prm_dev_inst = PRM_INSTANCE_UNKNOWN;
*/ */
void omap_prm_base_init(void) void omap_prm_base_init(void)
{ {
_prm_bases[OMAP4430_PRM_PARTITION] = prm_base; memcpy(&_prm_bases[OMAP4430_PRM_PARTITION], &prm_base,
_prm_bases[OMAP4430_PRCM_MPU_PARTITION] = prcm_mpu_base; sizeof(prm_base));
memcpy(&_prm_bases[OMAP4430_PRCM_MPU_PARTITION], &prcm_mpu_base,
sizeof(prcm_mpu_base));
} }
s32 omap4_prmst_get_prm_dev_inst(void) s32 omap4_prmst_get_prm_dev_inst(void)
@ -60,8 +62,8 @@ u32 omap4_prminst_read_inst_reg(u8 part, s16 inst, u16 idx)
{ {
BUG_ON(part >= OMAP4_MAX_PRCM_PARTITIONS || BUG_ON(part >= OMAP4_MAX_PRCM_PARTITIONS ||
part == OMAP4430_INVALID_PRCM_PARTITION || part == OMAP4430_INVALID_PRCM_PARTITION ||
!_prm_bases[part]); !_prm_bases[part].va);
return readl_relaxed(_prm_bases[part] + inst + idx); return readl_relaxed(_prm_bases[part].va + inst + idx);
} }
/* Write into a register in a PRM instance */ /* Write into a register in a PRM instance */
@ -69,8 +71,8 @@ void omap4_prminst_write_inst_reg(u32 val, u8 part, s16 inst, u16 idx)
{ {
BUG_ON(part >= OMAP4_MAX_PRCM_PARTITIONS || BUG_ON(part >= OMAP4_MAX_PRCM_PARTITIONS ||
part == OMAP4430_INVALID_PRCM_PARTITION || part == OMAP4430_INVALID_PRCM_PARTITION ||
!_prm_bases[part]); !_prm_bases[part].va);
writel_relaxed(val, _prm_bases[part] + inst + idx); writel_relaxed(val, _prm_bases[part].va + inst + idx);
} }
/* Read-modify-write a register in PRM. Caller must lock */ /* Read-modify-write a register in PRM. Caller must lock */