arm: dts: mt7623: update subsystem clock controller device nodes
Update MT7623 subsystem clock controllers, inlcuding mmsys, imgsys, vdecsys, g3dsys and bdpsys. Signed-off-by: Ryder Lee <ryder.lee@mediatek.com> Signed-off-by: Matthias Brugger <matthias.bgg@gmail.com>
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@ -692,6 +692,39 @@
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status = "disabled";
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};
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g3dsys: syscon@13000000 {
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compatible = "mediatek,mt7623-g3dsys",
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"mediatek,mt2701-g3dsys",
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"syscon";
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reg = <0 0x13000000 0 0x200>;
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#clock-cells = <1>;
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#reset-cells = <1>;
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};
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mmsys: syscon@14000000 {
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compatible = "mediatek,mt7623-mmsys",
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"mediatek,mt2701-mmsys",
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"syscon";
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reg = <0 0x14000000 0 0x1000>;
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#clock-cells = <1>;
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};
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imgsys: syscon@15000000 {
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compatible = "mediatek,mt7623-imgsys",
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"mediatek,mt2701-imgsys",
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"syscon";
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reg = <0 0x15000000 0 0x1000>;
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#clock-cells = <1>;
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};
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vdecsys: syscon@16000000 {
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compatible = "mediatek,mt7623-vdecsys",
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"mediatek,mt2701-vdecsys",
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"syscon";
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reg = <0 0x16000000 0 0x1000>;
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#clock-cells = <1>;
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};
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hifsys: syscon@1a000000 {
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compatible = "mediatek,mt7623-hifsys",
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"mediatek,mt2701-hifsys",
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@ -946,6 +979,14 @@
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power-domains = <&scpsys MT2701_POWER_DOMAIN_ETH>;
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status = "disabled";
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};
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bdpsys: syscon@1c000000 {
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compatible = "mediatek,mt7623-bdpsys",
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"mediatek,mt2701-bdpsys",
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"syscon";
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reg = <0 0x1c000000 0 0x1000>;
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#clock-cells = <1>;
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};
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};
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&pio {
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