drm/amd/display: add mechanism to skip DCN init
[Why] If optimized init is done in FW. DCN init be skipped in driver. This need to be communicated between driver and fw and maintain backwards compatibility. [How] Use DMUB scratch 0 bit 2 to indicate optimized init done in fw and use DMUB scatch 4 bit 0 to indicate drive supports the optimized flow so FW will perform it. Signed-off-by: Eric Yang <Eric.Yang2@amd.com> Reviewed-by: Tony Cheng <Tony.Cheng@amd.com> Acked-by: Rodrigo Siqueira <Rodrigo.Siqueira@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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c04bd16e48
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@ -2681,6 +2681,7 @@ void dc_interrupt_ack(struct dc *dc, enum dc_irq_source src)
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dal_irq_service_ack(dc->res_pool->irqs, src);
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}
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void dc_set_power_state(
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struct dc *dc,
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enum dc_acpi_cm_power_state power_state)
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@ -2692,9 +2693,6 @@ void dc_set_power_state(
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case DC_ACPI_CM_POWER_STATE_D0:
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dc_resource_state_construct(dc, dc->current_state);
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if (dc->ctx->dmub_srv)
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dc_dmub_srv_wait_phy_init(dc->ctx->dmub_srv);
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dc->hwss.init_hw(dc);
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if (dc->hwss.init_sys_ctx != NULL &&
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@ -106,29 +106,17 @@ void dc_dmub_srv_wait_idle(struct dc_dmub_srv *dc_dmub_srv)
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DC_ERROR("Error waiting for DMUB idle: status=%d\n", status);
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}
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void dc_dmub_srv_wait_phy_init(struct dc_dmub_srv *dc_dmub_srv)
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bool dc_dmub_srv_optimized_init_done(struct dc_dmub_srv *dc_dmub_srv)
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{
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struct dmub_srv *dmub = dc_dmub_srv->dmub;
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struct dc_context *dc_ctx = dc_dmub_srv->ctx;
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enum dmub_status status;
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struct dmub_srv *dmub;
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union dmub_fw_boot_status status;
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for (;;) {
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/* Wait up to a second for PHY init. */
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status = dmub_srv_wait_for_phy_init(dmub, 1000000);
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if (status == DMUB_STATUS_OK)
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/* Initialization OK */
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break;
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if (!dc_dmub_srv || !dc_dmub_srv->dmub)
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return false;
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DC_ERROR("DMCUB PHY init failed: status=%d\n", status);
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ASSERT(0);
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dmub = dc_dmub_srv->dmub;
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if (status != DMUB_STATUS_TIMEOUT)
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/*
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* Server likely initialized or we don't have
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* DMCUB HW support - this won't end.
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*/
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break;
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status = dmub->hw_funcs.get_fw_status(dmub);
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/* Continue spinning so we don't hang the ASIC. */
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}
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return status.bits.optimized_init_done;
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}
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@ -56,4 +56,6 @@ void dc_dmub_srv_wait_idle(struct dc_dmub_srv *dc_dmub_srv);
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void dc_dmub_srv_wait_phy_init(struct dc_dmub_srv *dc_dmub_srv);
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bool dc_dmub_srv_optimized_init_done(struct dc_dmub_srv *dc_dmub_srv);
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#endif /* _DMUB_DC_SRV_H_ */
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@ -1288,7 +1288,9 @@ void dcn10_init_hw(struct dc *dc)
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if (!dcb->funcs->is_accelerated_mode(dcb))
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hws->funcs.disable_vga(dc->hwseq);
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hws->funcs.bios_golden_init(dc);
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if (!dc_dmub_srv_optimized_init_done(dc->ctx->dmub_srv))
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hws->funcs.bios_golden_init(dc);
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if (dc->ctx->dc_bios->fw_info_valid) {
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res_pool->ref_clocks.xtalin_clock_inKhz =
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dc->ctx->dc_bios->fw_info.pll_info.crystal_frequency;
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@ -264,9 +264,10 @@ struct dmub_srv_hw_funcs {
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bool (*is_hw_init)(struct dmub_srv *dmub);
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bool (*is_phy_init)(struct dmub_srv *dmub);
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void (*enable_dmub_boot_options)(struct dmub_srv *dmub);
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union dmub_fw_boot_status (*get_fw_status)(struct dmub_srv *dmub);
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bool (*is_auto_load_done)(struct dmub_srv *dmub);
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void (*set_gpint)(struct dmub_srv *dmub,
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union dmub_gpint_data_register reg);
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@ -312,3 +312,18 @@ uint32_t dmub_dcn20_get_gpint_response(struct dmub_srv *dmub)
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{
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return REG_READ(DMCUB_SCRATCH7);
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}
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union dmub_fw_boot_status dmub_dcn20_get_fw_boot_status(struct dmub_srv *dmub)
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{
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union dmub_fw_boot_status status;
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status.all = REG_READ(DMCUB_SCRATCH0);
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return status;
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}
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void dmub_dcn20_enable_dmub_boot_options(struct dmub_srv *dmub)
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{
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union dmub_fw_boot_options boot_options = {0};
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REG_WRITE(DMCUB_SCRATCH14, boot_options.all);
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}
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@ -192,4 +192,8 @@ bool dmub_dcn20_is_gpint_acked(struct dmub_srv *dmub,
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uint32_t dmub_dcn20_get_gpint_response(struct dmub_srv *dmub);
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void dmub_dcn20_enable_dmub_boot_options(struct dmub_srv *dmub);
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union dmub_fw_boot_status dmub_dcn20_get_fw_boot_status(struct dmub_srv *dmub);
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#endif /* _DMUB_DCN20_H_ */
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@ -51,14 +51,4 @@ const struct dmub_srv_common_regs dmub_srv_dcn21_regs = {
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#undef DMUB_SF
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};
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/* Shared functions. */
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bool dmub_dcn21_is_auto_load_done(struct dmub_srv *dmub)
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{
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return (REG_READ(DMCUB_SCRATCH0) == 3);
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}
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bool dmub_dcn21_is_phy_init(struct dmub_srv *dmub)
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{
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return REG_READ(DMCUB_SCRATCH10) == 0;
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}
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@ -32,10 +32,4 @@
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extern const struct dmub_srv_common_regs dmub_srv_dcn21_regs;
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/* Hardware functions. */
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bool dmub_dcn21_is_auto_load_done(struct dmub_srv *dmub);
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bool dmub_dcn21_is_phy_init(struct dmub_srv *dmub);
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#endif /* _DMUB_DCN21_H_ */
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@ -153,18 +153,16 @@ static bool dmub_srv_hw_setup(struct dmub_srv *dmub, enum dmub_asic asic)
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funcs->set_gpint = dmub_dcn20_set_gpint;
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funcs->is_gpint_acked = dmub_dcn20_is_gpint_acked;
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funcs->get_gpint_response = dmub_dcn20_get_gpint_response;
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funcs->get_fw_status = dmub_dcn20_get_fw_boot_status;
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funcs->enable_dmub_boot_options = dmub_dcn20_enable_dmub_boot_options;
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if (asic == DMUB_ASIC_DCN21) {
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if (asic == DMUB_ASIC_DCN21)
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dmub->regs = &dmub_srv_dcn21_regs;
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funcs->is_auto_load_done = dmub_dcn21_is_auto_load_done;
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funcs->is_phy_init = dmub_dcn21_is_phy_init;
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}
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#ifdef CONFIG_DRM_AMD_DC_DCN3_0
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if (asic == DMUB_ASIC_DCN30) {
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dmub->regs = &dmub_srv_dcn30_regs;
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funcs->is_auto_load_done = dmub_dcn30_is_auto_load_done;
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funcs->backdoor_load = dmub_dcn30_backdoor_load;
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funcs->setup_windows = dmub_dcn30_setup_windows;
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}
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@ -454,6 +452,10 @@ enum dmub_status dmub_srv_hw_init(struct dmub_srv *dmub,
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dmub_rb_init(&dmub->inbox1_rb, &rb_params);
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}
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/* Report to DMUB what features are supported by current driver */
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if (dmub->hw_funcs.enable_dmub_boot_options)
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dmub->hw_funcs.enable_dmub_boot_options(dmub);
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if (dmub->hw_funcs.reset_release)
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dmub->hw_funcs.reset_release(dmub);
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@ -514,11 +516,10 @@ enum dmub_status dmub_srv_wait_for_auto_load(struct dmub_srv *dmub,
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if (!dmub->hw_init)
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return DMUB_STATUS_INVALID;
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if (!dmub->hw_funcs.is_auto_load_done)
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return DMUB_STATUS_OK;
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for (i = 0; i <= timeout_us; i += 100) {
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if (dmub->hw_funcs.is_auto_load_done(dmub))
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union dmub_fw_boot_status status = dmub->hw_funcs.get_fw_status(dmub);
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if (status.bits.dal_fw && status.bits.mailbox_rdy)
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return DMUB_STATUS_OK;
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udelay(100);
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@ -527,27 +528,6 @@ enum dmub_status dmub_srv_wait_for_auto_load(struct dmub_srv *dmub,
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return DMUB_STATUS_TIMEOUT;
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}
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enum dmub_status dmub_srv_wait_for_phy_init(struct dmub_srv *dmub,
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uint32_t timeout_us)
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{
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uint32_t i = 0;
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if (!dmub->hw_init)
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return DMUB_STATUS_INVALID;
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if (!dmub->hw_funcs.is_phy_init)
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return DMUB_STATUS_OK;
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for (i = 0; i <= timeout_us; i += 10) {
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if (dmub->hw_funcs.is_phy_init(dmub))
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return DMUB_STATUS_OK;
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udelay(10);
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}
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return DMUB_STATUS_TIMEOUT;
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}
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enum dmub_status dmub_srv_wait_for_idle(struct dmub_srv *dmub,
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uint32_t timeout_us)
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{
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