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drm/amdgpu: force pa_sc_tile_steering_override to 0 for navy_flounder 

pa_sc_tile_steering_override is only programmable for
gfx10.0/10.1/10.2, and navy_flounder has the same gfx10.3 IP
with sienna_cichlid.

Signed-off-by: Jiansong Chen <Jiansong.Chen@amd.com>
Reviewed-by: Tao Zhou <tao.zhou1@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
This commit is contained in:
Jiansong Chen 2020-04-13 16:11:27 +08:00 committed by Alex Deucher
parent c4a8b80286
commit 8f8463dddc
1 changed files with 2 additions and 1 deletions
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3
drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c
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@ -4496,7 +4496,8 @@ static u32 gfx_v10_0_init_pa_sc_tile_steering_override(struct amdgpu_device *ade
/* for ASICs that integrates GFX v10.3
* pa_sc_tile_steering_override should be set to 0 */
if (adev->asic_type == CHIP_SIENNA_CICHLID)
if (adev->asic_type == CHIP_SIENNA_CICHLID ||
adev->asic_type == CHIP_NAVY_FLOUNDER)
return 0;
/* init num_sc */