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net: stmmac: prepare irq_status for mtl 

This patch prepares mac irq status treatment for multiple queues.

Signed-off-by: Joao Pinto <jpinto@synopsys.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
This commit is contained in:
Joao Pinto 2017-03-10 18:24:57 +00:00 committed by David S. Miller
parent 29feff3900
commit 8f71a88d36
4 changed files with 33 additions and 16 deletions
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2
drivers/net/ethernet/stmicro/stmmac/common.h
View File

@ -472,6 +472,8 @@ struct stmmac_ops {
/* Handle extra events on specific interrupts hw dependent */ /* Handle extra events on specific interrupts hw dependent */
int (*host_irq_status)(struct mac_device_info *hw, int (*host_irq_status)(struct mac_device_info *hw,
struct stmmac_extra_stats *x); struct stmmac_extra_stats *x);
/* Handle MTL interrupts */
int (*host_mtl_irq_status)(struct mac_device_info *hw, u32 chan);
/* Multicast filter setting */ /* Multicast filter setting */
void (*set_filter)(struct mac_device_info *hw, struct net_device *dev); void (*set_filter)(struct mac_device_info *hw, struct net_device *dev);
/* Flow control setting */ /* Flow control setting */

2
drivers/net/ethernet/stmicro/stmmac/dwmac4.h
View File

@ -175,7 +175,7 @@ enum power_event {
#define MTL_OPERATION_RAA_WSP (0x1 << 2) #define MTL_OPERATION_RAA_WSP (0x1 << 2)
#define MTL_INT_STATUS 0x00000c20 #define MTL_INT_STATUS 0x00000c20
#define MTL_INT_Q0 BIT(0) #define MTL_INT_QX(x) BIT(x)
#define MTL_RXQ_DMA_MAP0 0x00000c30 /* queue 0 to 3 */ #define MTL_RXQ_DMA_MAP0 0x00000c30 /* queue 0 to 3 */
#define MTL_RXQ_DMA_MAP1 0x00000c34 /* queue 4 to 7 */ #define MTL_RXQ_DMA_MAP1 0x00000c34 /* queue 4 to 7 */

40
drivers/net/ethernet/stmicro/stmmac/dwmac4_core.c
View File

@ -416,11 +416,34 @@ static void dwmac4_phystatus(void __iomem *ioaddr, struct stmmac_extra_stats *x)
} }
} }
static int dwmac4_irq_mtl_status(struct mac_device_info *hw, u32 chan)
{
void __iomem *ioaddr = hw->pcsr;
u32 mtl_int_qx_status;
int ret = 0;
mtl_int_qx_status = readl(ioaddr + MTL_INT_STATUS);
/* Check MTL Interrupt */
if (mtl_int_qx_status & MTL_INT_QX(chan)) {
/* read Queue x Interrupt status */
u32 status = readl(ioaddr + MTL_CHAN_INT_CTRL(chan));
if (status & MTL_RX_OVERFLOW_INT) {
/* clear Interrupt */
writel(status | MTL_RX_OVERFLOW_INT,
ioaddr + MTL_CHAN_INT_CTRL(chan));
ret = CORE_IRQ_MTL_RX_OVERFLOW;
}
}
return ret;
}
static int dwmac4_irq_status(struct mac_device_info *hw, static int dwmac4_irq_status(struct mac_device_info *hw,
struct stmmac_extra_stats *x) struct stmmac_extra_stats *x)
{ {
void __iomem *ioaddr = hw->pcsr; void __iomem *ioaddr = hw->pcsr;
u32 mtl_int_qx_status;
u32 intr_status; u32 intr_status;
int ret = 0; int ret = 0;
@ -439,20 +462,6 @@ static int dwmac4_irq_status(struct mac_device_info *hw,
x->irq_receive_pmt_irq_n++; x->irq_receive_pmt_irq_n++;
} }
mtl_int_qx_status = readl(ioaddr + MTL_INT_STATUS);
/* Check MTL Interrupt: Currently only one queue is used: Q0. */
if (mtl_int_qx_status & MTL_INT_Q0) {
/* read Queue 0 Interrupt status */
u32 status = readl(ioaddr + MTL_CHAN_INT_CTRL(STMMAC_CHAN0));
if (status & MTL_RX_OVERFLOW_INT) {
/* clear Interrupt */
writel(status | MTL_RX_OVERFLOW_INT,
ioaddr + MTL_CHAN_INT_CTRL(STMMAC_CHAN0));
ret = CORE_IRQ_MTL_RX_OVERFLOW;
}
}
dwmac_pcs_isr(ioaddr, GMAC_PCS_BASE, intr_status, x); dwmac_pcs_isr(ioaddr, GMAC_PCS_BASE, intr_status, x);
if (intr_status & PCS_RGSMIIIS_IRQ) if (intr_status & PCS_RGSMIIIS_IRQ)
dwmac4_phystatus(ioaddr, x); dwmac4_phystatus(ioaddr, x);
@ -554,6 +563,7 @@ static const struct stmmac_ops dwmac4_ops = {
.map_mtl_to_dma = dwmac4_map_mtl_dma, .map_mtl_to_dma = dwmac4_map_mtl_dma,
.dump_regs = dwmac4_dump_regs, .dump_regs = dwmac4_dump_regs,
.host_irq_status = dwmac4_irq_status, .host_irq_status = dwmac4_irq_status,
.host_mtl_irq_status = dwmac4_irq_mtl_status,
.flow_ctrl = dwmac4_flow_ctrl, .flow_ctrl = dwmac4_flow_ctrl,
.pmt = dwmac4_pmt, .pmt = dwmac4_pmt,
.set_umac_addr = dwmac4_set_umac_addr, .set_umac_addr = dwmac4_set_umac_addr,

5
drivers/net/ethernet/stmicro/stmmac/stmmac_main.c
View File

@ -2901,6 +2901,11 @@ static irqreturn_t stmmac_interrupt(int irq, void *dev_id)
if ((priv->plat->has_gmac) || (priv->plat->has_gmac4)) { if ((priv->plat->has_gmac) || (priv->plat->has_gmac4)) {
int status = priv->hw->mac->host_irq_status(priv->hw, int status = priv->hw->mac->host_irq_status(priv->hw,
&priv->xstats); &priv->xstats);
if (priv->synopsys_id >= DWMAC_CORE_4_00)
status |= priv->hw->mac->host_mtl_irq_status(priv->hw,
STMMAC_CHAN0);
if (unlikely(status)) { if (unlikely(status)) {
/* For LPI we need to save the tx status */ /* For LPI we need to save the tx status */
if (status & CORE_IRQ_TX_PATH_IN_LPI_MODE) if (status & CORE_IRQ_TX_PATH_IN_LPI_MODE)