drm/amd/powerplay: add function set_clock_limit for Rv.
Sets floors for various clocks depending on current requirements. Signed-off-by: Rex Zhu <Rex.Zhu@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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@ -44,6 +44,8 @@
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static const unsigned long PhwRaven_Magic = (unsigned long) PHM_Cz_Magic;
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static const unsigned long PhwRaven_Magic = (unsigned long) PHM_Cz_Magic;
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int rv_display_clock_voltage_request(struct pp_hwmgr *hwmgr,
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struct pp_display_clock_request *clock_req);
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struct phm_vq_budgeting_record rv_vqtable[] = {
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struct phm_vq_budgeting_record rv_vqtable[] = {
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/* _TBD
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/* _TBD
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@ -232,9 +234,61 @@ static int rv_construct_boot_state(struct pp_hwmgr *hwmgr)
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return 0;
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return 0;
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}
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}
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static int rv_tf_set_isp_clock_limit(struct pp_hwmgr *hwmgr, void *input,
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static int rv_tf_set_clock_limit(struct pp_hwmgr *hwmgr, void *input,
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void *output, void *storage, int result)
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void *output, void *storage, int result)
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{
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{
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struct rv_hwmgr *rv_data = (struct rv_hwmgr *)(hwmgr->backend);
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struct PP_Clocks clocks = {0};
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struct pp_display_clock_request clock_req;
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clocks.dcefClock = hwmgr->display_config.min_dcef_set_clk;
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clocks.dcefClockInSR = hwmgr->display_config.min_dcef_deep_sleep_set_clk;
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clock_req.clock_type = amd_pp_dcf_clock;
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clock_req.clock_freq_in_khz = clocks.dcefClock * 10;
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if (clocks.dcefClock == 0 && clocks.dcefClockInSR == 0)
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clock_req.clock_freq_in_khz = rv_data->dcf_actual_hard_min_freq;
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PP_ASSERT_WITH_CODE(!rv_display_clock_voltage_request(hwmgr, &clock_req),
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"Attempt to set DCF Clock Failed!", return -EINVAL);
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if(rv_data->need_min_deep_sleep_dcefclk && 0 != clocks.dcefClockInSR)
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smum_send_msg_to_smc_with_parameter(hwmgr->smumgr,
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PPSMC_MSG_SetMinDeepSleepDcefclk,
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clocks.dcefClockInSR / 100);
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/*
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if(!rv_data->isp_tileA_power_gated || !rv_data->isp_tileB_power_gated) {
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if ((hwmgr->ispArbiter.iclk != 0) && (rv_data->ISPActualHardMinFreq != (hwmgr->ispArbiter.iclk / 100) )) {
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smum_send_msg_to_smc_with_parameter(hwmgr->smumgr,
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PPSMC_MSG_SetHardMinIspclkByFreq, hwmgr->ispArbiter.iclk / 100);
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rv_read_arg_from_smc(hwmgr->smumgr, &rv_data->ISPActualHardMinFreq),
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}
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} */
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if((hwmgr->gfx_arbiter.sclk_hard_min != 0) &&
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((hwmgr->gfx_arbiter.sclk_hard_min / 100) != rv_data->soc_actual_hard_min_freq)) {
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smum_send_msg_to_smc_with_parameter(hwmgr->smumgr,
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PPSMC_MSG_SetHardMinSocclkByFreq,
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hwmgr->gfx_arbiter.sclk_hard_min / 100);
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rv_read_arg_from_smc(hwmgr->smumgr, &rv_data->soc_actual_hard_min_freq);
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}
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if ((hwmgr->gfx_arbiter.gfxclk != 0) &&
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(rv_data->gfx_actual_soft_min_freq != (hwmgr->gfx_arbiter.gfxclk))) {
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smum_send_msg_to_smc_with_parameter(hwmgr->smumgr,
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PPSMC_MSG_SetMinVideoGfxclkFreq,
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hwmgr->gfx_arbiter.gfxclk / 100);
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rv_read_arg_from_smc(hwmgr->smumgr, &rv_data->gfx_actual_soft_min_freq);
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}
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if ((hwmgr->gfx_arbiter.fclk != 0) &&
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(rv_data->fabric_actual_soft_min_freq != (hwmgr->gfx_arbiter.fclk / 100))) {
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smum_send_msg_to_smc_with_parameter(hwmgr->smumgr,
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PPSMC_MSG_SetMinVideoFclkFreq,
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hwmgr->gfx_arbiter.fclk / 100);
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rv_read_arg_from_smc(hwmgr->smumgr, &rv_data->fabric_actual_soft_min_freq);
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}
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return 0;
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return 0;
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}
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}
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@ -254,7 +308,7 @@ static int rv_tf_set_num_active_display(struct pp_hwmgr *hwmgr, void *input,
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}
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}
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static const struct phm_master_table_item rv_set_power_state_list[] = {
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static const struct phm_master_table_item rv_set_power_state_list[] = {
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{ NULL, rv_tf_set_isp_clock_limit },
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{ NULL, rv_tf_set_clock_limit },
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{ NULL, rv_tf_set_num_active_display },
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{ NULL, rv_tf_set_num_active_display },
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{ }
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{ }
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};
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};
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@ -276,6 +276,11 @@ struct rv_hwmgr {
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bool isp_tileB_power_gated;
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bool isp_tileB_power_gated;
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uint32_t isp_actual_hard_min_freq;
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uint32_t isp_actual_hard_min_freq;
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uint32_t soc_actual_hard_min_freq;
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uint32_t soc_actual_hard_min_freq;
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uint32_t dcf_actual_hard_min_freq;
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uint32_t f_actual_hard_min_freq;
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uint32_t fabric_actual_soft_min_freq;
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uint32_t gfx_actual_soft_min_freq;
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bool vcn_power_gated;
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bool vcn_power_gated;
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bool vcn_dpg_mode;
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bool vcn_dpg_mode;
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@ -286,6 +291,7 @@ struct rv_hwmgr {
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DpmClocks_t clock_table;
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DpmClocks_t clock_table;
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uint32_t active_process_mask;
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uint32_t active_process_mask;
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bool need_min_deep_sleep_dcefclk; /* disabled by default */
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};
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};
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struct pp_hwmgr;
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struct pp_hwmgr;
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