MMC core:
- Clear flags before allowing to retune MMC host: - sdhci: Clear unused bounce buffer at DMA mmap error path - sdhci: Fix warning message when accessing RPMB in HS400 mode - sdhci-of-arasan: Use clock-frequency property to update clk_xin - mtk-sd: Fixup compatible string for MT8195 -----BEGIN PGP SIGNATURE----- iQJLBAABCgA1FiEEugLDXPmKSktSkQsV/iaEJXNYjCkFAmDi3jYXHHVsZi5oYW5z c29uQGxpbmFyby5vcmcACgkQ/iaEJXNYjClqXg/+KGzL6qRBvoy8UcwVI650a8WM QKRyYzHUjp8DQh8zpPu1e49VeILKdZokxrlIa4z/E/HVgYMkGOJ/lE/7TUCDNDS9 WwxT4M8ToIK7T45wKNpYtLS+AYR3dQk/H7Y0hsXEDulGki37OvTfykhI+0gxBpWj Beigw2RAnXsw/vXmLHLwJHYOF3zO1T2bN+O96dA14XXyhVaWmxb9xA06PwjSsLhL 7Sk2ydFPrZW2H13INw4pjPJetzEI3aiuWmi2udwHAaVxtvh2MDX7253i4JbHmWFS mIEusnibTi91TUVrVbPMXbWJe/DApbNLPXjtzzmivQRD/RPZlCLVYR6CusUhxs6B bkOVIsUV8zlnuPg3UcZq7kHZ2WkWD3QFsBZoQ1hFAeBGTQcYb00IGHYHQUGVAeCo T237CKK0bLVqaZzoGjcsVk22L878hW1mfcimM1XW0P7Rc9xLKHpBBFH7cswYvnVV DRR8EU0bneSjefkF8HW3+gUNJNVJJTkpYipe81j1aDLN8vj0fPYgFRqDLOAaBHRC pFsYOrm0exkzmn7XSvZsOI4WZ7xHCnCQoUZNNOz3nw6jZUSHvf0BmuROx8ZKQy3d jCoG6OaslvjzAZ7ORmzJk0c7FsD/JWyrW8xdzC9ot3P+PRshpSPvZGG+JfmrCeZ/ DCE5gIRuc37dose92M4= =Rucm -----END PGP SIGNATURE----- Merge tag 'mmc-v5.14-2' of git://git.kernel.org/pub/scm/linux/kernel/git/ulfh/mmc Pull MMC fixes from Ulf Hansson "MMC core: - Clear flags before allowing to retune MMC host: - sdhci: Clear unused bounce buffer at DMA mmap error path - sdhci: Fix warning message when accessing RPMB in HS400 mode - sdhci-of-arasan: Use clock-frequency property to update clk_xin - mtk-sd: Fixup compatible string for MT8195" * tag 'mmc-v5.14-2' of git://git.kernel.org/pub/scm/linux/kernel/git/ulfh/mmc: mmc: sdhci: Fix warning message when accessing RPMB in HS400 mode dt-bindings: mmc: change compatiable string for MT8195 mmc host IP mmc: sdhci: Clear unused bounce buffer at DMA mmap error path phy: intel: Fix for warnings due to EMMC clock 175Mhz change in FIP mmc: sdhci-of-arasan: Use clock-frequency property to update clk_xin mmc: core: clear flags before allowing to retune
This commit is contained in:
commit
8f3f2ccf3c
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@ -31,6 +31,8 @@ properties:
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- const: mediatek,mt2701-mmc
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- items:
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- const: mediatek,mt8192-mmc
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- const: mediatek,mt8183-mmc
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- items:
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- const: mediatek,mt8195-mmc
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- const: mediatek,mt8183-mmc
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@ -937,11 +937,14 @@ int mmc_execute_tuning(struct mmc_card *card)
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err = host->ops->execute_tuning(host, opcode);
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if (err)
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if (err) {
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pr_err("%s: tuning execution failed: %d\n",
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mmc_hostname(host), err);
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else
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} else {
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host->retune_now = 0;
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host->need_retune = 0;
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mmc_retune_enable(host);
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}
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return err;
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}
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@ -1542,6 +1542,8 @@ static int sdhci_arasan_probe(struct platform_device *pdev)
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}
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}
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sdhci_get_of_property(pdev);
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sdhci_arasan->clk_ahb = devm_clk_get(dev, "clk_ahb");
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if (IS_ERR(sdhci_arasan->clk_ahb)) {
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ret = dev_err_probe(dev, PTR_ERR(sdhci_arasan->clk_ahb),
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@ -1561,14 +1563,22 @@ static int sdhci_arasan_probe(struct platform_device *pdev)
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goto err_pltfm_free;
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}
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/* If clock-frequency property is set, use the provided value */
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if (pltfm_host->clock &&
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pltfm_host->clock != clk_get_rate(clk_xin)) {
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ret = clk_set_rate(clk_xin, pltfm_host->clock);
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if (ret) {
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dev_err(&pdev->dev, "Failed to set SD clock rate\n");
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goto clk_dis_ahb;
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}
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}
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ret = clk_prepare_enable(clk_xin);
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if (ret) {
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dev_err(dev, "Unable to enable SD clock.\n");
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goto clk_dis_ahb;
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}
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sdhci_get_of_property(pdev);
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if (of_property_read_bool(np, "xlnx,fails-without-test-cd"))
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sdhci_arasan->quirks |= SDHCI_ARASAN_QUIRK_FORCE_CDTEST;
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@ -1812,6 +1812,10 @@ static u16 sdhci_get_preset_value(struct sdhci_host *host)
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u16 preset = 0;
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switch (host->timing) {
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case MMC_TIMING_MMC_HS:
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case MMC_TIMING_SD_HS:
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preset = sdhci_readw(host, SDHCI_PRESET_FOR_HIGH_SPEED);
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break;
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case MMC_TIMING_UHS_SDR12:
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preset = sdhci_readw(host, SDHCI_PRESET_FOR_SDR12);
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break;
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@ -4072,9 +4076,13 @@ static void sdhci_allocate_bounce_buffer(struct sdhci_host *host)
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bounce_size,
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DMA_BIDIRECTIONAL);
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ret = dma_mapping_error(mmc_dev(mmc), host->bounce_addr);
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if (ret)
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if (ret) {
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devm_kfree(mmc_dev(mmc), host->bounce_buffer);
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host->bounce_buffer = NULL;
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/* Again fall back to max_segs == 1 */
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return;
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}
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host->bounce_buffer_size = bounce_size;
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/* Lie about this since we're bouncing */
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@ -255,6 +255,7 @@
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/* 60-FB reserved */
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#define SDHCI_PRESET_FOR_HIGH_SPEED 0x64
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#define SDHCI_PRESET_FOR_SDR12 0x66
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#define SDHCI_PRESET_FOR_SDR25 0x68
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#define SDHCI_PRESET_FOR_SDR50 0x6A
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@ -95,7 +95,8 @@ static int keembay_emmc_phy_power(struct phy *phy, bool on_off)
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else
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freqsel = 0x0;
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if (mhz < 50 || mhz > 200)
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/* Check for EMMC clock rate*/
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if (mhz > 175)
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dev_warn(&phy->dev, "Unsupported rate: %d MHz\n", mhz);
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/*
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