ARM: brcmstb: Add entry for 7255
Add in BCM7255 entry and reorder entries to keep ascending order. Also moved 7278 cause it was out of order. Signed-off-by: Justin Chen <justinpopo6@gmail.com> Signed-off-by: Florian Fainelli <f.fainelli@gmail.com>
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@ -26,8 +26,9 @@
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#define UARTA_3390 REG_PHYS_ADDR(0x40a900)
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#define UARTA_7250 REG_PHYS_ADDR(0x40b400)
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#define UARTA_7260 REG_PHYS_ADDR(0x40c000)
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#define UARTA_7268 UARTA_7260
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#define UARTA_7255 REG_PHYS_ADDR(0x40c000)
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#define UARTA_7260 UARTA_7255
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#define UARTA_7268 UARTA_7255
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#define UARTA_7271 UARTA_7268
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#define UARTA_7278 REG_PHYS_ADDR_V7(0x40c000)
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#define UARTA_7364 REG_PHYS_ADDR(0x40b000)
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@ -82,15 +83,16 @@ ARM_BE8( rev \rv, \rv )
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/* Chip specific detection starts here */
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20: checkuart(\rp, \rv, 0x33900000, 3390)
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21: checkuart(\rp, \rv, 0x72500000, 7250)
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22: checkuart(\rp, \rv, 0x72600000, 7260)
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23: checkuart(\rp, \rv, 0x72680000, 7268)
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24: checkuart(\rp, \rv, 0x72710000, 7271)
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25: checkuart(\rp, \rv, 0x73640000, 7364)
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26: checkuart(\rp, \rv, 0x73660000, 7366)
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27: checkuart(\rp, \rv, 0x07437100, 74371)
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28: checkuart(\rp, \rv, 0x74390000, 7439)
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29: checkuart(\rp, \rv, 0x74450000, 7445)
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30: checkuart(\rp, \rv, 0x72780000, 7278)
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22: checkuart(\rp, \rv, 0x72550000, 7255)
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23: checkuart(\rp, \rv, 0x72600000, 7260)
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24: checkuart(\rp, \rv, 0x72680000, 7268)
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25: checkuart(\rp, \rv, 0x72710000, 7271)
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26: checkuart(\rp, \rv, 0x72780000, 7278)
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27: checkuart(\rp, \rv, 0x73640000, 7364)
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28: checkuart(\rp, \rv, 0x73660000, 7366)
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29: checkuart(\rp, \rv, 0x07437100, 74371)
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30: checkuart(\rp, \rv, 0x74390000, 7439)
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31: checkuart(\rp, \rv, 0x74450000, 7445)
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/* No valid UART found */
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90: mov \rp, #0
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