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powerpc/eeh: rename EEH from "extended" to "enhanced" error handling 

IBM online documentation for EEH uses "extended error handling" and
"enhanced error handling" to refer to the same thing, in different
places.  The only place mentioning it as "enhanced error handling" in the
kernel is the MAINTAINERS file, and it's "extended" in some documentation.

IBM originally defined EEH as "enhanced error handling", so standardise
all mentions of EEH to use that term.

Signed-off-by: Russell Currey <ruscur@russell.cc>
Acked-by: Gavin Shan <gwshan@linux.vnet.ibm.com>
Signed-off-by: Michael Ellerman <mpe@ellerman.id.au>
This commit is contained in:
Russell Currey 2016-02-16 23:06:05 +11:00 committed by Michael Ellerman
parent b4c6afdc3a
commit 8ee26530bb
2 changed files with 2 additions and 2 deletions
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2
Documentation/powerpc/eeh-pci-error-recovery.txt
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@ -12,7 +12,7 @@ Overview:
The IBM POWER-based pSeries and iSeries computers include PCI bus The IBM POWER-based pSeries and iSeries computers include PCI bus
controller chips that have extended capabilities for detecting and controller chips that have extended capabilities for detecting and
reporting a large variety of PCI bus error conditions. These features reporting a large variety of PCI bus error conditions. These features
go under the name of "EEH", for "Extended Error Handling". The EEH go under the name of "EEH", for "Enhanced Error Handling". The EEH
hardware features allow PCI bus errors to be cleared and a PCI hardware features allow PCI bus errors to be cleared and a PCI
card to be "rebooted", without also having to reboot the operating card to be "rebooted", without also having to reboot the operating
system. system.

2
arch/powerpc/kernel/eeh.c
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@ -48,7 +48,7 @@
/** Overview: /** Overview:
* EEH, or "Extended Error Handling" is a PCI bridge technology for * EEH, or "Enhanced Error Handling" is a PCI bridge technology for
* dealing with PCI bus errors that can't be dealt with within the * dealing with PCI bus errors that can't be dealt with within the
* usual PCI framework, except by check-stopping the CPU. Systems * usual PCI framework, except by check-stopping the CPU. Systems
* that are designed for high-availability/reliability cannot afford * that are designed for high-availability/reliability cannot afford