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clk: tegra: dfll: Update kerneldoc 

The kerneldoc for struct tegra_dfll_soc_data is stale. Update it to
match the current structure definition.

Signed-off-by: Thierry Reding <treding@nvidia.com>
This commit is contained in:
Thierry Reding 2016-04-08 14:57:09 +02:00
parent 7970973018
commit 8eaaae9937
1 changed files with 5 additions and 5 deletions
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10
drivers/clk/tegra/clk-dfll.h
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@ -24,15 +24,14 @@
/**
* struct tegra_dfll_soc_data - SoC-specific hooks/integration for the DFLL driver
* @opp_dev: struct device * that holds the OPP table for the DFLL
* @dev: struct device * that holds the OPP table for the DFLL
* @min_millivolts: minimum voltage (in mV) that the DFLL can operate
* @tune0_low: DFLL tuning register 0 (low voltage range)
* @tune0_high: DFLL tuning register 0 (high voltage range)
* @tune1: DFLL tuning register 1
* @assert_dvco_reset: fn ptr to place the DVCO in reset
* @deassert_dvco_reset: fn ptr to release the DVCO reset
* @set_clock_trimmers_high: fn ptr to tune clock trimmers for high voltage
* @set_clock_trimmers_low: fn ptr to tune clock trimmers for low voltage
* @init_clock_trimmers: callback to initialize clock trimmers
* @set_clock_trimmers_high: callback to tune clock trimmers for high voltage
* @set_clock_trimmers_low: callback to tune clock trimmers for low voltage
*/
struct tegra_dfll_soc_data {
struct device *dev;
@ -40,6 +39,7 @@ struct tegra_dfll_soc_data {
u32 tune0_low;
u32 tune0_high;
u32 tune1;
void (*init_clock_trimmers)(void);
void (*set_clock_trimmers_high)(void);
void (*set_clock_trimmers_low)(void);