The device tree changes for the continued RealView DT
support. -----BEGIN PGP SIGNATURE----- Version: GnuPG v1 iQIcBAABAgAGBQJWb9NkAAoJEEEQszewGV1zVIIP/iRfWwsmuOscmw7hl25E5h1U KWb8Q0b71vkDDe5rhCGZzahdosX+BVnP2gE4Ft0p1ekgFkIoGEL4qCfiMgs8cOHn RxraRkkS7U9CpT9OpOyew96VyPA5yoOWLes0VxUJ9vNGgE79UoaRpMzNYnpIBAVE vfZXT1JFXvz9ZoWL6jnehsafrLSqJpXCcbMA28i6Wx4BMSSjkXp0MGLxp5eDjebM EWuxfgLpdoZvTM6Uwzs1KEk/DcyqgdfwrOCHvtd66lKvTZSzkvc82jOF18s2tjZs 355eWuEvsyVHAak+QWW1QGxayXGKhbPjPmNUHXRrBE4y1FGncJtnrKGe9eNimvhQ ge8/EAeImqg8LrQ4Rea9wNh/VmVn+BHZgShHRI6BdzIOiCKLhyRWQJ4lgcmLf53C r8SfRL2lOasGvgfBEAb30a9JRVGSPyCWufqmQ6LQtrCwBu7VHzsl/9VrJemZN9TD dd5FboClHZUOgJA9la1uT/5qlIA3bfucJ3cHWPYFGbv5pErdNWpBI+GNQhN0QTQq be8gCM5MvSg1zXflBbvD+afZvmfDZl2DAc80asGywp5vumpH2nj4RgkZpJoisb/H V9hvlcPVYOvCrgTRXrTNyRU6d0VZc2DHMZqYP04KqmYJKBS4sAyBiEpLyZ8CeCQA BLvA139rl6/MqQo5sIkQ =De8M -----END PGP SIGNATURE----- Merge tag 'realview-base-armsoc-2-tag' of git://git.kernel.org/pub/scm/linux/kernel/git/linusw/linux-integrator into next/dt Merge "Realview DT files" from Linus Walleij: The device tree changes for the continued RealView DT support. * tag 'realview-base-armsoc-2-tag' of git://git.kernel.org/pub/scm/linux/kernel/git/linusw/linux-integrator: ARM: realview: add device tree for PB11MPCore clk: add ARM syscon ICST device tree bindings ARM: add DT bindings for the ARM11MPCore CPU cluster
This commit is contained in:
Arnd Bergmann
commit
8ea1c981b6
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@ -10,10 +10,13 @@ References:
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Revision r2p0
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- Cortex-A5: see DDI0434B Cortex-A5 MPCore Technical Reference Manual
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Revision r0p1
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- ARM11 MPCore: see DDI0360F ARM 11 MPCore Processor Technical Reference
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Manial Revision r2p0
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- compatible : Should be:
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"arm,cortex-a9-scu"
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"arm,cortex-a5-scu"
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"arm,arm11mp-scu"
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- reg : Specify the base address and the size of the SCU register window.
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@ -0,0 +1,40 @@
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ARM System Controller ICST clocks
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The ICS525 and ICS307 oscillators are produced by Integrated Devices
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Technology (IDT). ARM integrated these oscillators deeply into their
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reference designs by adding special control registers that manage such
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oscillators to their system controllers.
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The ARM system controller contains logic to serialize and initialize
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an ICST clock request after a write to the 32 bit register at an offset
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into the system controller. Furthermore, to even be able to alter one of
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these frequencies, the system controller must first be unlocked by
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writing a special token to another offset in the system controller.
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The ICST oscillator must be provided inside a system controller node.
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Required properties:
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- lock-offset: the offset address into the system controller where the
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unlocking register is located
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- vco-offset: the offset address into the system controller where the
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ICST control register is located (even 32 bit address)
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- compatible: must be one of "arm,syscon-icst525" or "arm,syscon-icst307"
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- #clock-cells: must be <0>
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- clocks: parent clock, since the ICST needs a parent clock to derive its
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frequency from, this attribute is compulsory.
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Example:
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syscon: syscon@10000000 {
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compatible = "syscon";
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reg = <0x10000000 0x1000>;
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oscclk0: osc0@0c {
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compatible = "arm,syscon-icst307";
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#clock-cells = <0>;
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lock-offset = <0x20>;
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vco-offset = <0x0c>;
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clocks = <&xtal24mhz>;
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};
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(...)
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};
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@ -519,7 +519,8 @@ dtb-$(CONFIG_ARCH_QCOM) += \
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qcom-msm8960-cdp.dtb \
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qcom-msm8974-sony-xperia-honami.dtb
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dtb-$(CONFIG_ARCH_REALVIEW) += \
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arm-realview-pb1176.dtb
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arm-realview-pb1176.dtb \
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arm-realview-pb11mp.dtb
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dtb-$(CONFIG_ARCH_ROCKCHIP) += \
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rk3036-evb.dtb \
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rk3066a-bqcurie2.dtb \
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@ -0,0 +1,668 @@
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/*
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* Copyright 2015 Linaro Ltd
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*
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* Permission is hereby granted, free of charge, to any person obtaining a copy
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* of this software and associated documentation files (the "Software"), to deal
|
||||
* in the Software without restriction, including without limitation the rights
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||||
* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
|
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* copies of the Software, and to permit persons to whom the Software is
|
||||
* furnished to do so, subject to the following conditions:
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||||
*
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||||
* The above copyright notice and this permission notice shall be included in
|
||||
* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
|
||||
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
|
||||
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
|
||||
* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
|
||||
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
|
||||
* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
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* THE SOFTWARE.
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*/
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/dts-v1/;
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#include <dt-bindings/interrupt-controller/irq.h>
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#include <dt-bindings/gpio/gpio.h>
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#include "skeleton.dtsi"
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/ {
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model = "ARM RealView PB11MPcore";
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compatible = "arm,realview-pb11mp";
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chosen { };
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aliases {
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serial0 = &pb11mp_serial0;
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serial1 = &pb11mp_serial1;
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serial2 = &pb11mp_serial2;
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serial3 = &pb11mp_serial3;
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};
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memory {
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/*
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* The PB11MPCore has 512 MiB memory @ 0x70000000
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* and the first 256 are also remapped @ 0x00000000
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*/
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reg = <0x70000000 0x20000000>;
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};
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cpus {
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#address-cells = <1>;
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#size-cells = <0>;
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enable-method = "arm,realview-smp";
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MP11_0: cpu@0 {
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device_type = "cpu";
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compatible = "arm,arm11mpcore";
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reg = <0>;
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next-level-cache = <&L2>;
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};
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MP11_1: cpu@1 {
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device_type = "cpu";
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compatible = "arm,arm11mpcore";
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reg = <1>;
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next-level-cache = <&L2>;
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};
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MP11_2: cpu@2 {
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device_type = "cpu";
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compatible = "arm,arm11mpcore";
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reg = <2>;
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next-level-cache = <&L2>;
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};
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MP11_3: cpu@3 {
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device_type = "cpu";
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compatible = "arm,arm11mpcore";
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reg = <3>;
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next-level-cache = <&L2>;
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};
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};
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/* Primary TestChip GIC synthesized with the CPU */
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intc_tc11mp: interrupt-controller@1f000100 {
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compatible = "arm,tc11mp-gic";
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#interrupt-cells = <3>;
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#address-cells = <1>;
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interrupt-controller;
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reg = <0x1f001000 0x1000>,
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<0x1f000100 0x100>;
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};
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L2: l2-cache {
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compatible = "arm,l220-cache";
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reg = <0x1f002000 0x1000>;
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interrupt-parent = <&intc_tc11mp>;
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interrupts = <0 29 IRQ_TYPE_LEVEL_HIGH>,
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<0 30 IRQ_TYPE_LEVEL_HIGH>,
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<0 31 IRQ_TYPE_LEVEL_HIGH>;
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cache-unified;
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cache-level = <2>;
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};
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scu@1f000000 {
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compatible = "arm,arm11mp-scu";
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reg = <0x1f000000 0x100>;
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};
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timer@1f000600 {
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compatible = "arm,arm11mp-twd-timer";
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reg = <0x1f000600 0x20>;
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interrupt-parent = <&intc_tc11mp>;
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interrupts = <1 13 0xf04>;
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};
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watchdog@1f000620 {
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compatible = "arm,arm11mp-twd-wdt";
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reg = <0x1f000620 0x20>;
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interrupt-parent = <&intc_tc11mp>;
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interrupts = <1 14 0xf04>;
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};
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/* PMU with one IRQ line per core */
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pmu {
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compatible = "arm,arm11mpcore-pmu";
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interrupt-parent = <&intc_tc11mp>;
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interrupts = <0 17 IRQ_TYPE_LEVEL_HIGH>,
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<0 18 IRQ_TYPE_LEVEL_HIGH>,
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<0 19 IRQ_TYPE_LEVEL_HIGH>,
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<0 20 IRQ_TYPE_LEVEL_HIGH>;
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interrupt-affinity = <&MP11_0>, <&MP11_1>, <&MP11_2>, <&MP11_3>;
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};
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/* The voltage to the MMC card is hardwired at 3.3V */
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vmmc: fixedregulator@0 {
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compatible = "regulator-fixed";
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regulator-name = "vmmc";
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regulator-min-microvolt = <3300000>;
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regulator-max-microvolt = <3300000>;
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regulator-boot-on;
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};
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veth: fixedregulator@0 {
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compatible = "regulator-fixed";
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regulator-name = "veth";
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regulator-min-microvolt = <3300000>;
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regulator-max-microvolt = <3300000>;
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regulator-boot-on;
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};
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xtal24mhz: xtal24mhz@24M {
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#clock-cells = <0>;
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compatible = "fixed-clock";
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clock-frequency = <24000000>;
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};
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refclk32khz: refclk32khz {
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compatible = "fixed-clock";
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#clock-cells = <0>;
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clock-frequency = <32768>;
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};
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timclk: timclk@1M {
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#clock-cells = <0>;
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compatible = "fixed-factor-clock";
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clock-div = <24>;
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clock-mult = <1>;
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clocks = <&xtal24mhz>;
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};
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mclk: mclk@24M {
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#clock-cells = <0>;
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compatible = "fixed-factor-clock";
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clock-div = <1>;
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clock-mult = <1>;
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clocks = <&xtal24mhz>;
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};
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kmiclk: kmiclk@24M {
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#clock-cells = <0>;
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compatible = "fixed-factor-clock";
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clock-div = <1>;
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clock-mult = <1>;
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clocks = <&xtal24mhz>;
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};
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sspclk: sspclk@24M {
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#clock-cells = <0>;
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compatible = "fixed-factor-clock";
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clock-div = <1>;
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clock-mult = <1>;
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clocks = <&xtal24mhz>;
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};
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uartclk: uartclk@24M {
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#clock-cells = <0>;
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compatible = "fixed-factor-clock";
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clock-div = <1>;
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clock-mult = <1>;
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clocks = <&xtal24mhz>;
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};
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wdogclk: wdogclk@24M {
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#clock-cells = <0>;
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compatible = "fixed-factor-clock";
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clock-div = <1>;
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clock-mult = <1>;
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clocks = <&xtal24mhz>;
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};
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/* FIXME: this actually hangs off the PLL clocks */
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pclk: pclk@0 {
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#clock-cells = <0>;
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compatible = "fixed-clock";
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clock-frequency = <0>;
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};
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flash0@40000000 {
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/* 2 * 32MiB NOR Flash memory */
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compatible = "arm,vexpress-flash", "cfi-flash";
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reg = <0x40000000 0x04000000>;
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bank-width = <4>;
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};
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flash1@44000000 {
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// 2 * 32MiB NOR Flash memory
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compatible = "arm,vexpress-flash", "cfi-flash";
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reg = <0x44000000 0x04000000>;
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bank-width = <4>;
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};
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soc {
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#address-cells = <1>;
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#size-cells = <1>;
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compatible = "arm,realview-pb11mp-soc", "simple-bus";
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regmap = <&pb11mp_syscon>;
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ranges;
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pb11mp_syscon: syscon@10000000 {
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compatible = "arm,realview-pb11mp-syscon", "syscon", "simple-mfd";
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reg = <0x10000000 0x1000>;
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led@08.0 {
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compatible = "register-bit-led";
|
||||
offset = <0x08>;
|
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mask = <0x01>;
|
||||
label = "versatile:0";
|
||||
linux,default-trigger = "heartbeat";
|
||||
default-state = "on";
|
||||
};
|
||||
led@08.1 {
|
||||
compatible = "register-bit-led";
|
||||
offset = <0x08>;
|
||||
mask = <0x02>;
|
||||
label = "versatile:1";
|
||||
linux,default-trigger = "mmc0";
|
||||
default-state = "off";
|
||||
};
|
||||
led@08.2 {
|
||||
compatible = "register-bit-led";
|
||||
offset = <0x08>;
|
||||
mask = <0x04>;
|
||||
label = "versatile:2";
|
||||
linux,default-trigger = "cpu0";
|
||||
default-state = "off";
|
||||
};
|
||||
led@08.3 {
|
||||
compatible = "register-bit-led";
|
||||
offset = <0x08>;
|
||||
mask = <0x08>;
|
||||
label = "versatile:3";
|
||||
linux,default-trigger = "cpu1";
|
||||
default-state = "off";
|
||||
};
|
||||
led@08.4 {
|
||||
compatible = "register-bit-led";
|
||||
offset = <0x08>;
|
||||
mask = <0x10>;
|
||||
label = "versatile:4";
|
||||
linux,default-trigger = "cpu2";
|
||||
default-state = "off";
|
||||
};
|
||||
led@08.5 {
|
||||
compatible = "register-bit-led";
|
||||
offset = <0x08>;
|
||||
mask = <0x20>;
|
||||
label = "versatile:5";
|
||||
linux,default-trigger = "cpu3";
|
||||
default-state = "off";
|
||||
};
|
||||
led@08.6 {
|
||||
compatible = "register-bit-led";
|
||||
offset = <0x08>;
|
||||
mask = <0x40>;
|
||||
label = "versatile:6";
|
||||
default-state = "off";
|
||||
};
|
||||
led@08.7 {
|
||||
compatible = "register-bit-led";
|
||||
offset = <0x08>;
|
||||
mask = <0x80>;
|
||||
label = "versatile:7";
|
||||
default-state = "off";
|
||||
};
|
||||
|
||||
oscclk0: osc0@0c {
|
||||
compatible = "arm,syscon-icst307";
|
||||
#clock-cells = <0>;
|
||||
lock-offset = <0x20>;
|
||||
vco-offset = <0x0C>;
|
||||
clocks = <&xtal24mhz>;
|
||||
};
|
||||
oscclk1: osc1@10 {
|
||||
compatible = "arm,syscon-icst307";
|
||||
#clock-cells = <0>;
|
||||
lock-offset = <0x20>;
|
||||
vco-offset = <0x10>;
|
||||
clocks = <&xtal24mhz>;
|
||||
};
|
||||
oscclk2: osc2@14 {
|
||||
compatible = "arm,syscon-icst307";
|
||||
#clock-cells = <0>;
|
||||
lock-offset = <0x20>;
|
||||
vco-offset = <0x14>;
|
||||
clocks = <&xtal24mhz>;
|
||||
};
|
||||
oscclk3: osc3@18 {
|
||||
compatible = "arm,syscon-icst307";
|
||||
#clock-cells = <0>;
|
||||
lock-offset = <0x20>;
|
||||
vco-offset = <0x18>;
|
||||
clocks = <&xtal24mhz>;
|
||||
};
|
||||
oscclk4: osc4@1c {
|
||||
compatible = "arm,syscon-icst307";
|
||||
#clock-cells = <0>;
|
||||
lock-offset = <0x20>;
|
||||
vco-offset = <0x1c>;
|
||||
clocks = <&xtal24mhz>;
|
||||
};
|
||||
oscclk5: osc5@d4 {
|
||||
compatible = "arm,syscon-icst307";
|
||||
#clock-cells = <0>;
|
||||
lock-offset = <0x20>;
|
||||
vco-offset = <0xd4>;
|
||||
clocks = <&xtal24mhz>;
|
||||
};
|
||||
oscclk6: osc6@d8 {
|
||||
compatible = "arm,syscon-icst307";
|
||||
#clock-cells = <0>;
|
||||
lock-offset = <0x20>;
|
||||
vco-offset = <0xd8>;
|
||||
clocks = <&xtal24mhz>;
|
||||
};
|
||||
};
|
||||
|
||||
sp810_syscon: sysctl@10001000 {
|
||||
compatible = "arm,sp810", "arm,primecell";
|
||||
reg = <0x10001000 0x1000>;
|
||||
clocks = <&refclk32khz>, <&timclk>, <&xtal24mhz>;
|
||||
clock-names = "refclk", "timclk", "apb_pclk";
|
||||
#clock-cells = <1>;
|
||||
clock-output-names = "timerclk0",
|
||||
"timerclk1",
|
||||
"timerclk2",
|
||||
"timerclk3";
|
||||
assigned-clocks = <&sp810_syscon 0>,
|
||||
<&sp810_syscon 1>,
|
||||
<&sp810_syscon 2>,
|
||||
<&sp810_syscon 3>;
|
||||
assigned-clock-parents = <&timclk>,
|
||||
<&timclk>,
|
||||
<&timclk>,
|
||||
<&timclk>;
|
||||
};
|
||||
|
||||
i2c0: i2c@10002000 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
compatible = "arm,versatile-i2c";
|
||||
reg = <0x10002000 0x1000>;
|
||||
|
||||
rtc@68 {
|
||||
compatible = "dallas,ds1338";
|
||||
reg = <0x68>;
|
||||
};
|
||||
};
|
||||
|
||||
aaci: aaci@10004000 {
|
||||
compatible = "arm,pl041", "arm,primecell";
|
||||
reg = <0x10004000 0x1000>;
|
||||
interrupt-parent = <&intc_tc11mp>;
|
||||
interrupts = <0 0 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&pclk>;
|
||||
clock-names = "apb_pclk";
|
||||
};
|
||||
|
||||
mci: mmcsd@10005000 {
|
||||
compatible = "arm,pl18x", "arm,primecell";
|
||||
reg = <0x10005000 0x1000>;
|
||||
interrupt-parent = <&intc_tc11mp>;
|
||||
interrupts = <0 14 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<0 15 IRQ_TYPE_LEVEL_HIGH>;
|
||||
/* Due to frequent FIFO overruns, use just 500 kHz */
|
||||
max-frequency = <500000>;
|
||||
bus-width = <4>;
|
||||
cap-sd-highspeed;
|
||||
cap-mmc-highspeed;
|
||||
clocks = <&mclk>, <&pclk>;
|
||||
clock-names = "mclk", "apb_pclk";
|
||||
vmmc-supply = <&vmmc>;
|
||||
cd-gpios = <&gpio2 0 GPIO_ACTIVE_LOW>;
|
||||
wp-gpios = <&gpio2 1 GPIO_ACTIVE_HIGH>;
|
||||
};
|
||||
|
||||
kmi0: kmi@10006000 {
|
||||
compatible = "arm,pl050", "arm,primecell";
|
||||
reg = <0x10006000 0x1000>;
|
||||
interrupt-parent = <&intc_tc11mp>;
|
||||
interrupts = <0 7 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&kmiclk>, <&pclk>;
|
||||
clock-names = "KMIREFCLK", "apb_pclk";
|
||||
};
|
||||
|
||||
kmi1: kmi@10007000 {
|
||||
compatible = "arm,pl050", "arm,primecell";
|
||||
reg = <0x10007000 0x1000>;
|
||||
interrupt-parent = <&intc_tc11mp>;
|
||||
interrupts = <0 8 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&kmiclk>, <&pclk>;
|
||||
clock-names = "KMIREFCLK", "apb_pclk";
|
||||
};
|
||||
|
||||
pb11mp_serial0: serial@10009000 {
|
||||
compatible = "arm,pl011", "arm,primecell";
|
||||
reg = <0x10009000 0x1000>;
|
||||
interrupt-parent = <&intc_tc11mp>;
|
||||
interrupts = <0 4 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&uartclk>, <&pclk>;
|
||||
clock-names = "uartclk", "apb_pclk";
|
||||
};
|
||||
|
||||
pb11mp_serial1: serial@1000a000 {
|
||||
compatible = "arm,pl011", "arm,primecell";
|
||||
reg = <0x1000a000 0x1000>;
|
||||
interrupt-parent = <&intc_tc11mp>;
|
||||
interrupts = <0 5 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&uartclk>, <&pclk>;
|
||||
clock-names = "uartclk", "apb_pclk";
|
||||
};
|
||||
|
||||
pb11mp_serial2: serial@1000b000 {
|
||||
compatible = "arm,pl011", "arm,primecell";
|
||||
reg = <0x1000b000 0x1000>;
|
||||
interrupt-parent = <&intc_pb11mp>;
|
||||
interrupts = <0 14 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&uartclk>, <&pclk>;
|
||||
clock-names = "uartclk", "apb_pclk";
|
||||
};
|
||||
|
||||
pb11mp_serial3: serial@1000c000 {
|
||||
compatible = "arm,pl011", "arm,primecell";
|
||||
reg = <0x1000c000 0x1000>;
|
||||
interrupt-parent = <&intc_pb11mp>;
|
||||
interrupts = <0 15 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&uartclk>, <&pclk>;
|
||||
clock-names = "uartclk", "apb_pclk";
|
||||
};
|
||||
|
||||
ssp@1000d000 {
|
||||
compatible = "arm,pl022", "arm,primecell";
|
||||
reg = <0x1000d000 0x1000>;
|
||||
interrupt-parent = <&intc_pb11mp>;
|
||||
interrupts = <0 11 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&sspclk>, <&pclk>;
|
||||
clock-names = "SSPCLK", "apb_pclk";
|
||||
};
|
||||
|
||||
watchdog@1000f000 {
|
||||
compatible = "arm,sp805", "arm,primecell";
|
||||
reg = <0x1000f000 0x1000>;
|
||||
interrupt-parent = <&intc_pb11mp>;
|
||||
interrupts = <0 0 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&wdogclk>, <&pclk>;
|
||||
clock-names = "wdogclk", "apb_pclk";
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
watchdog@10010000 {
|
||||
compatible = "arm,sp805", "arm,primecell";
|
||||
reg = <0x10010000 0x1000>;
|
||||
interrupt-parent = <&intc_pb11mp>;
|
||||
interrupts = <0 0 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&wdogclk>, <&pclk>;
|
||||
clock-names = "wdogclk", "apb_pclk";
|
||||
};
|
||||
|
||||
timer01: timer@10011000 {
|
||||
compatible = "arm,sp804", "arm,primecell";
|
||||
reg = <0x10011000 0x1000>;
|
||||
interrupt-parent = <&intc_tc11mp>;
|
||||
interrupts = <0 1 IRQ_TYPE_LEVEL_HIGH>;
|
||||
arm,sp804-has-irq = <1>;
|
||||
clocks = <&sp810_syscon 0>,
|
||||
<&sp810_syscon 1>,
|
||||
<&pclk>;
|
||||
clock-names = "timerclk0",
|
||||
"timerclk1",
|
||||
"apb_pclk";
|
||||
};
|
||||
|
||||
timer23: timer@10012000 {
|
||||
compatible = "arm,sp804", "arm,primecell";
|
||||
reg = <0x10012000 0x1000>;
|
||||
interrupt-parent = <&intc_tc11mp>;
|
||||
interrupts = <0 2 IRQ_TYPE_LEVEL_HIGH>;
|
||||
arm,sp804-has-irq = <1>;
|
||||
clocks = <&sp810_syscon 2>,
|
||||
<&sp810_syscon 3>,
|
||||
<&pclk>;
|
||||
clock-names = "timerclk2",
|
||||
"timerclk3",
|
||||
"apb_pclk";
|
||||
};
|
||||
|
||||
gpio0: gpio@10013000 {
|
||||
compatible = "arm,pl061", "arm,primecell";
|
||||
reg = <0x10013000 0x1000>;
|
||||
gpio-controller;
|
||||
interrupt-parent = <&intc_pb11mp>;
|
||||
interrupts = <0 6 IRQ_TYPE_LEVEL_HIGH>;
|
||||
#gpio-cells = <2>;
|
||||
interrupt-controller;
|
||||
#interrupt-cells = <2>;
|
||||
clocks = <&pclk>;
|
||||
clock-names = "apb_pclk";
|
||||
};
|
||||
|
||||
gpio1: gpio@10014000 {
|
||||
compatible = "arm,pl061", "arm,primecell";
|
||||
reg = <0x10014000 0x1000>;
|
||||
gpio-controller;
|
||||
interrupt-parent = <&intc_pb11mp>;
|
||||
interrupts = <0 7 IRQ_TYPE_LEVEL_HIGH>;
|
||||
#gpio-cells = <2>;
|
||||
interrupt-controller;
|
||||
#interrupt-cells = <2>;
|
||||
clocks = <&pclk>;
|
||||
clock-names = "apb_pclk";
|
||||
};
|
||||
|
||||
gpio2: gpio@10015000 {
|
||||
compatible = "arm,pl061", "arm,primecell";
|
||||
reg = <0x10015000 0x1000>;
|
||||
gpio-controller;
|
||||
interrupt-parent = <&intc_pb11mp>;
|
||||
interrupts = <0 8 IRQ_TYPE_LEVEL_HIGH>;
|
||||
#gpio-cells = <2>;
|
||||
interrupt-controller;
|
||||
#interrupt-cells = <2>;
|
||||
clocks = <&pclk>;
|
||||
clock-names = "apb_pclk";
|
||||
};
|
||||
|
||||
rtc: rtc@10017000 {
|
||||
compatible = "arm,pl031", "arm,primecell";
|
||||
reg = <0x10017000 0x1000>;
|
||||
interrupt-parent = <&intc_tc11mp>;
|
||||
interrupts = <0 6 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&pclk>;
|
||||
clock-names = "apb_pclk";
|
||||
};
|
||||
|
||||
timer45: timer@10018000 {
|
||||
compatible = "arm,sp804", "arm,primecell";
|
||||
reg = <0x10018000 0x1000>;
|
||||
clocks = <&timclk>, <&pclk>;
|
||||
clock-names = "timer", "apb_pclk";
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
timer67: timer@10019000 {
|
||||
compatible = "arm,sp804", "arm,primecell";
|
||||
reg = <0x10019000 0x1000>;
|
||||
clocks = <&timclk>, <&pclk>;
|
||||
clock-names = "timer", "apb_pclk";
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
|
||||
clcd@10020000 {
|
||||
compatible = "arm,pl111", "arm,primecell";
|
||||
reg = <0x10020000 0x1000>;
|
||||
interrupt-parent = <&intc_pb11mp>;
|
||||
interrupt-names = "combined";
|
||||
interrupts = <0 23 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&oscclk4>, <&pclk>;
|
||||
clock-names = "clcdclk", "apb_pclk";
|
||||
max-memory-bandwidth = <130000000>; /* 16bpp @ 63.5MHz */
|
||||
|
||||
port {
|
||||
clcd_pads: endpoint {
|
||||
remote-endpoint = <&clcd_panel>;
|
||||
arm,pl11x,tft-r0g0b0-pads = <0 8 16>;
|
||||
};
|
||||
};
|
||||
|
||||
panel {
|
||||
compatible = "panel-dpi";
|
||||
|
||||
port {
|
||||
clcd_panel: endpoint {
|
||||
remote-endpoint = <&clcd_pads>;
|
||||
};
|
||||
};
|
||||
|
||||
panel-timing {
|
||||
clock-frequency = <63500127>;
|
||||
hactive = <1024>;
|
||||
hback-porch = <152>;
|
||||
hfront-porch = <48>;
|
||||
hsync-len = <104>;
|
||||
vactive = <768>;
|
||||
vback-porch = <23>;
|
||||
vfront-porch = <3>;
|
||||
vsync-len = <4>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
/*
|
||||
* This GIC on the Platform Baseboard is cascaded off the
|
||||
* TestChip GIC
|
||||
*/
|
||||
intc_pb11mp: interrupt-controller@1e000000 {
|
||||
compatible = "arm,arm11mp-gic";
|
||||
#interrupt-cells = <3>;
|
||||
#address-cells = <1>;
|
||||
interrupt-controller;
|
||||
reg = <0x1e001000 0x1000>,
|
||||
<0x1e000000 0x100>;
|
||||
interrupt-parent = <&intc_tc11mp>;
|
||||
interrupts = <0 10 IRQ_TYPE_LEVEL_HIGH>;
|
||||
};
|
||||
|
||||
/* SMSC 9118 ethernet with PHY and EEPROM */
|
||||
ethernet@4e000000 {
|
||||
compatible = "smsc,lan9118", "smsc,lan9115";
|
||||
reg = <0x4e000000 0x10000>;
|
||||
interrupt-parent = <&intc_tc11mp>;
|
||||
interrupts = <0 9 IRQ_TYPE_LEVEL_HIGH>;
|
||||
phy-mode = "mii";
|
||||
reg-io-width = <4>;
|
||||
smsc,irq-active-high;
|
||||
smsc,irq-push-pull;
|
||||
vdd33a-supply = <&veth>;
|
||||
vddvario-supply = <&veth>;
|
||||
};
|
||||
|
||||
usb@4f000000 {
|
||||
compatible = "nxp,usb-isp1761";
|
||||
reg = <0x4f000000 0x20000>;
|
||||
interrupt-parent = <&intc_tc11mp>;
|
||||
interrupts = <0 3 IRQ_TYPE_LEVEL_HIGH>;
|
||||
port1-otg;
|
||||
};
|
||||
};
|
||||
};
|
||||
Loading…
Reference in New Issue