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CLK: Add basic infrastructure for Pistachio clocks 

Add helpers for registering clocks and clock providers on Pistachio.

Signed-off-by: Andrew Bresticker <abrestic@chromium.org>
Cc: Mike Turquette <mturquette@linaro.org>
Cc: Stephen Boyd <sboyd@codeaurora.org>
Cc: devicetree@vger.kernel.org
Cc: linux-mips@linux-mips.org
Cc: linux-kernel@vger.kernel.org
Cc: Ezequiel Garcia <ezequiel.garcia@imgtec.com>
Cc: James Hartley <james.hartley@imgtec.com>
Cc: James Hogan <james.hogan@imgtec.com>
Acked-by: Stephen Boyd <sboyd@codeaurora.org>
Patchwork: https://patchwork.linux-mips.org/patch/9318/
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
This commit is contained in:
Andrew Bresticker 2015-02-24 19:56:02 -08:00 committed by Ralf Baechle
parent 1006e3c931
commit 8e4b7721f6
4 changed files with 266 additions and 0 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

1
drivers/clk/Makefile
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@ -54,6 +54,7 @@ obj-$(CONFIG_ARCH_MMP) += mmp/
endif
obj-$(CONFIG_PLAT_ORION) += mvebu/
obj-$(CONFIG_ARCH_MXS) += mxs/
obj-$(CONFIG_MACH_PISTACHIO) += pistachio/
obj-$(CONFIG_COMMON_CLK_PXA) += pxa/
obj-$(CONFIG_COMMON_CLK_QCOM) += qcom/
obj-$(CONFIG_ARCH_ROCKCHIP) += rockchip/

1
drivers/clk/pistachio/Makefile Normal file
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@ -0,0 +1 @@
obj-y += clk.o

140
drivers/clk/pistachio/clk.c Normal file
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@ -0,0 +1,140 @@
/*
* Copyright (C) 2014 Google, Inc.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms and conditions of the GNU General Public License,
* version 2, as published by the Free Software Foundation.
*/
#include <linux/clk-provider.h>
#include <linux/kernel.h>
#include <linux/of.h>
#include <linux/of_address.h>
#include <linux/slab.h>
#include "clk.h"
struct pistachio_clk_provider *
pistachio_clk_alloc_provider(struct device_node *node, unsigned int num_clks)
{
struct pistachio_clk_provider *p;
p = kzalloc(sizeof(*p), GFP_KERNEL);
if (!p)
return p;
p->clk_data.clks = kcalloc(num_clks, sizeof(struct clk *), GFP_KERNEL);
if (!p->clk_data.clks)
goto free_provider;
p->clk_data.clk_num = num_clks;
p->node = node;
p->base = of_iomap(node, 0);
if (!p->base) {
pr_err("Failed to map clock provider registers\n");
goto free_clks;
}
return p;
free_clks:
kfree(p->clk_data.clks);
free_provider:
kfree(p);
return NULL;
}
void pistachio_clk_register_provider(struct pistachio_clk_provider *p)
{
unsigned int i;
for (i = 0; i < p->clk_data.clk_num; i++) {
if (IS_ERR(p->clk_data.clks[i]))
pr_warn("Failed to register clock %d: %ld\n", i,
PTR_ERR(p->clk_data.clks[i]));
}
of_clk_add_provider(p->node, of_clk_src_onecell_get, &p->clk_data);
}
void pistachio_clk_register_gate(struct pistachio_clk_provider *p,
struct pistachio_gate *gate,
unsigned int num)
{
struct clk *clk;
unsigned int i;
for (i = 0; i < num; i++) {
clk = clk_register_gate(NULL, gate[i].name, gate[i].parent,
CLK_SET_RATE_PARENT,
p->base + gate[i].reg, gate[i].shift,
0, NULL);
p->clk_data.clks[gate[i].id] = clk;
}
}
void pistachio_clk_register_mux(struct pistachio_clk_provider *p,
struct pistachio_mux *mux,
unsigned int num)
{
struct clk *clk;
unsigned int i;
for (i = 0; i < num; i++) {
clk = clk_register_mux(NULL, mux[i].name, mux[i].parents,
mux[i].num_parents,
CLK_SET_RATE_NO_REPARENT,
p->base + mux[i].reg, mux[i].shift,
get_count_order(mux[i].num_parents),
0, NULL);
p->clk_data.clks[mux[i].id] = clk;
}
}
void pistachio_clk_register_div(struct pistachio_clk_provider *p,
struct pistachio_div *div,
unsigned int num)
{
struct clk *clk;
unsigned int i;
for (i = 0; i < num; i++) {
clk = clk_register_divider(NULL, div[i].name, div[i].parent,
0, p->base + div[i].reg, 0,
div[i].width, div[i].div_flags,
NULL);
p->clk_data.clks[div[i].id] = clk;
}
}
void pistachio_clk_register_fixed_factor(struct pistachio_clk_provider *p,
struct pistachio_fixed_factor *ff,
unsigned int num)
{
struct clk *clk;
unsigned int i;
for (i = 0; i < num; i++) {
clk = clk_register_fixed_factor(NULL, ff[i].name, ff[i].parent,
0, 1, ff[i].div);
p->clk_data.clks[ff[i].id] = clk;
}
}
void pistachio_clk_force_enable(struct pistachio_clk_provider *p,
unsigned int *clk_ids, unsigned int num)
{
unsigned int i;
int err;
for (i = 0; i < num; i++) {
struct clk *clk = p->clk_data.clks[clk_ids[i]];
if (IS_ERR(clk))
continue;
err = clk_prepare_enable(clk);
if (err)
pr_err("Failed to enable clock %s: %d\n",
__clk_get_name(clk), err);
}
}

124
drivers/clk/pistachio/clk.h Normal file
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@ -0,0 +1,124 @@
/*
* Copyright (C) 2014 Google, Inc.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms and conditions of the GNU General Public License,
* version 2, as published by the Free Software Foundation.
*/
#ifndef __PISTACHIO_CLK_H
#define __PISTACHIO_CLK_H
#include <linux/clk-provider.h>
struct pistachio_gate {
unsigned int id;
unsigned long reg;
unsigned int shift;
const char *name;
const char *parent;
};
#define GATE(_id, _name, _pname, _reg, _shift) \
{ \
.id = _id, \
.reg = _reg, \
.shift = _shift, \
.name = _name, \
.parent = _pname, \
}
struct pistachio_mux {
unsigned int id;
unsigned long reg;
unsigned int shift;
unsigned int num_parents;
const char *name;
const char **parents;
};
#define PNAME(x) static const char *x[] __initconst
#define MUX(_id, _name, _pnames, _reg, _shift) \
{ \
.id = _id, \
.reg = _reg, \
.shift = _shift, \
.name = _name, \
.parents = _pnames, \
.num_parents = ARRAY_SIZE(_pnames) \
}
struct pistachio_div {
unsigned int id;
unsigned long reg;
unsigned int width;
unsigned int div_flags;
const char *name;
const char *parent;
};
#define DIV(_id, _name, _pname, _reg, _width) \
{ \
.id = _id, \
.reg = _reg, \
.width = _width, \
.div_flags = 0, \
.name = _name, \
.parent = _pname, \
}
#define DIV_F(_id, _name, _pname, _reg, _width, _div_flags) \
{ \
.id = _id, \
.reg = _reg, \
.width = _width, \
.div_flags = _div_flags, \
.name = _name, \
.parent = _pname, \
}
struct pistachio_fixed_factor {
unsigned int id;
unsigned int div;
const char *name;
const char *parent;
};
#define FIXED_FACTOR(_id, _name, _pname, _div) \
{ \
.id = _id, \
.div = _div, \
.name = _name, \
.parent = _pname, \
}
struct pistachio_clk_provider {
struct device_node *node;
void __iomem *base;
struct clk_onecell_data clk_data;
};
extern struct pistachio_clk_provider *
pistachio_clk_alloc_provider(struct device_node *node, unsigned int num_clks);
extern void pistachio_clk_register_provider(struct pistachio_clk_provider *p);
extern void pistachio_clk_register_gate(struct pistachio_clk_provider *p,
struct pistachio_gate *gate,
unsigned int num);
extern void pistachio_clk_register_mux(struct pistachio_clk_provider *p,
struct pistachio_mux *mux,
unsigned int num);
extern void pistachio_clk_register_div(struct pistachio_clk_provider *p,
struct pistachio_div *div,
unsigned int num);
extern void
pistachio_clk_register_fixed_factor(struct pistachio_clk_provider *p,
struct pistachio_fixed_factor *ff,
unsigned int num);
extern void pistachio_clk_force_enable(struct pistachio_clk_provider *p,
unsigned int *clk_ids, unsigned int num);
#endif