From 8de81c89d0a1aff777057dd78c3f5e4c654494f1 Mon Sep 17 00:00:00 2001 From: Philipp Zabel Date: Mon, 4 Feb 2019 16:29:56 +0100 Subject: [PATCH] ARM: dts: pfla02: add ksz9031 clock skew values The pfla02 SoM has a Micrel KSZ9031RNX ethernet phy connected to the FEC, which needs RX and TX clock skew settings to compensate for differences in line length. The skew values are taken from barebox commit 4c65c20f1071 ("ARM: pfla02: Set new ethernet phy tx timings"), which is based on patches originally provided by Phytec: TX_CLK line is approx. 54mm longer than other TX lines which adds a delay of 0.36ns. RGMII need a delay of min. 1.0ns. This mean we have to add a delay of 0.64ns. We choose 0.78 to have a little gap. This can be done by setting GTX pad skew value to 11100 Also add a delay for the RX delay lines, needed for the Duallite variant. => Set register 2.8 (RGMII Clock Pad Skew) to 0x039F. Cc: Christian Hemp Signed-off-by: Philipp Zabel Signed-off-by: Marco Felsch Signed-off-by: Shawn Guo --- arch/arm/boot/dts/imx6qdl-phytec-pfla02.dtsi | 13 +++++++++++++ 1 file changed, 13 insertions(+) diff --git a/arch/arm/boot/dts/imx6qdl-phytec-pfla02.dtsi b/arch/arm/boot/dts/imx6qdl-phytec-pfla02.dtsi index 1bfa41e01a0c..433bf09a1954 100644 --- a/arch/arm/boot/dts/imx6qdl-phytec-pfla02.dtsi +++ b/arch/arm/boot/dts/imx6qdl-phytec-pfla02.dtsi @@ -89,10 +89,23 @@ &fec { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_enet>; + phy-handle = <ðphy>; phy-mode = "rgmii"; phy-reset-gpios = <&gpio3 23 GPIO_ACTIVE_LOW>; phy-supply = <&vdd_eth_io_reg>; status = "disabled"; + + fec_mdio: mdio { + #address-cells = <1>; + #size-cells = <0>; + + ethphy: ethernet-phy@0 { + compatible = "ethernet-phy-ieee802.3-c22"; + reg = <0>; + txc-skew-ps = <1680>; + rxc-skew-ps = <1860>; + }; + }; }; &gpmi {