amd64_edac: cleanup rest of amd64_dump_misc_regs
Clarify bitfields description, add PCI config function/offset names to registers for easy reference, simplify code layout, remove unneeded info. Signed-off-by: Borislav Petkov <borislav.petkov@amd.com>
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@ -862,32 +862,23 @@ static void amd64_dump_misc_regs(struct amd64_pvt *pvt)
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amd64_dump_dramcfg_low(pvt->dclr0, 0);
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debugf1(" online-spare: 0x%8.08x\n", pvt->online_spare);
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debugf1("F3xB0 (Online Spare): 0x%08x\n", pvt->online_spare);
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if (boot_cpu_data.x86 == 0xf) {
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debugf1(" dhar: 0x%8.08x Base=0x%08x Offset=0x%08x\n",
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pvt->dhar, dhar_base(pvt->dhar),
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k8_dhar_offset(pvt->dhar));
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debugf1(" DramHoleValid=%s\n",
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(pvt->dhar & DHAR_VALID) ? "True" : "False");
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debugf1("F1xF0 (DRAM Hole Address): 0x%08x, base: 0x%08x, "
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"offset: 0x%08x\n",
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pvt->dhar,
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dhar_base(pvt->dhar),
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(boot_cpu_data.x86 == 0xf) ? k8_dhar_offset(pvt->dhar)
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: f10_dhar_offset(pvt->dhar));
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debugf1(" dbam-dkt: 0x%8.08x\n", pvt->dbam0);
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debugf1(" DramHoleValid: %s\n",
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(pvt->dhar & DHAR_VALID) ? "yes" : "no");
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/* everything below this point is Fam10h and above */
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/* everything below this point is Fam10h and above */
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if (boot_cpu_data.x86 == 0xf)
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return;
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} else {
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debugf1(" dhar: 0x%8.08x Base=0x%08x Offset=0x%08x\n",
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pvt->dhar, dhar_base(pvt->dhar),
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f10_dhar_offset(pvt->dhar));
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debugf1(" DramMemHoistValid=%s DramHoleValid=%s\n",
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(pvt->dhar & F10_DRAM_MEM_HOIST_VALID) ?
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"True" : "False",
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(pvt->dhar & DHAR_VALID) ?
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"True" : "False");
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}
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/* Only if NOT ganged does dcl1 have valid info */
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/* Only if NOT ganged does dclr1 have valid info */
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if (!dct_ganging_enabled(pvt))
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amd64_dump_dramcfg_low(pvt->dclr1, 1);
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