usb: musb: ux500: add dma glue layer for ux500
Unaligned sizes and buffers are not supported and they will be filtered out by is_compatible(). Signed-off-by: Mian Yousaf Kaukab <mian.yousaf.kaukab@stericsson.com> Signed-off-by: Felipe Balbi <balbi@ti.com>
This commit is contained in:
Mian Yousaf Kaukab
Felipe Balbi
parent
e3c496f9b3
commit
8dcc8f72e3
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@ -0,0 +1,422 @@
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/*
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* drivers/usb/musb/ux500_dma.c
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*
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* U8500 and U5500 DMA support code
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*
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* Copyright (C) 2009 STMicroelectronics
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* Copyright (C) 2011 ST-Ericsson SA
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* Authors:
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* Mian Yousaf Kaukab <mian.yousaf.kaukab@stericsson.com>
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* Praveena Nadahally <praveen.nadahally@stericsson.com>
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* Rajaram Regupathy <ragupathy.rajaram@stericsson.com>
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*
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* This program is free software: you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation, either version 2 of the License, or
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* (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program. If not, see <http://www.gnu.org/licenses/>.
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*/
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#include <linux/device.h>
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#include <linux/interrupt.h>
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#include <linux/platform_device.h>
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#include <linux/dma-mapping.h>
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#include <linux/dmaengine.h>
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#include <linux/pfn.h>
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#include <mach/usb.h>
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#include "musb_core.h"
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struct ux500_dma_channel {
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struct dma_channel channel;
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struct ux500_dma_controller *controller;
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struct musb_hw_ep *hw_ep;
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struct work_struct channel_work;
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struct dma_chan *dma_chan;
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unsigned int cur_len;
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dma_cookie_t cookie;
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u8 ch_num;
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u8 is_tx;
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u8 is_allocated;
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};
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struct ux500_dma_controller {
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struct dma_controller controller;
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struct ux500_dma_channel rx_channel[UX500_MUSB_DMA_NUM_RX_CHANNELS];
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struct ux500_dma_channel tx_channel[UX500_MUSB_DMA_NUM_TX_CHANNELS];
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u32 num_rx_channels;
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u32 num_tx_channels;
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void *private_data;
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dma_addr_t phy_base;
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};
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/* Work function invoked from DMA callback to handle tx transfers. */
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static void ux500_tx_work(struct work_struct *data)
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{
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struct ux500_dma_channel *ux500_channel = container_of(data,
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struct ux500_dma_channel, channel_work);
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struct musb_hw_ep *hw_ep = ux500_channel->hw_ep;
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struct musb *musb = hw_ep->musb;
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unsigned long flags;
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DBG(4, "DMA tx transfer done on hw_ep=%d\n", hw_ep->epnum);
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spin_lock_irqsave(&musb->lock, flags);
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ux500_channel->channel.actual_len = ux500_channel->cur_len;
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ux500_channel->channel.status = MUSB_DMA_STATUS_FREE;
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musb_dma_completion(musb, hw_ep->epnum,
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ux500_channel->is_tx);
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spin_unlock_irqrestore(&musb->lock, flags);
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}
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/* Work function invoked from DMA callback to handle rx transfers. */
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static void ux500_rx_work(struct work_struct *data)
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{
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struct ux500_dma_channel *ux500_channel = container_of(data,
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struct ux500_dma_channel, channel_work);
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struct musb_hw_ep *hw_ep = ux500_channel->hw_ep;
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struct musb *musb = hw_ep->musb;
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unsigned long flags;
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DBG(4, "DMA rx transfer done on hw_ep=%d\n", hw_ep->epnum);
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spin_lock_irqsave(&musb->lock, flags);
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ux500_channel->channel.actual_len = ux500_channel->cur_len;
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ux500_channel->channel.status = MUSB_DMA_STATUS_FREE;
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musb_dma_completion(musb, hw_ep->epnum,
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ux500_channel->is_tx);
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spin_unlock_irqrestore(&musb->lock, flags);
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}
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void ux500_dma_callback(void *private_data)
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{
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struct dma_channel *channel = (struct dma_channel *)private_data;
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struct ux500_dma_channel *ux500_channel = channel->private_data;
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schedule_work(&ux500_channel->channel_work);
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}
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static bool ux500_configure_channel(struct dma_channel *channel,
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u16 packet_sz, u8 mode,
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dma_addr_t dma_addr, u32 len)
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{
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struct ux500_dma_channel *ux500_channel = channel->private_data;
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struct musb_hw_ep *hw_ep = ux500_channel->hw_ep;
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struct dma_chan *dma_chan = ux500_channel->dma_chan;
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struct dma_async_tx_descriptor *dma_desc;
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enum dma_data_direction direction;
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struct scatterlist sg;
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struct dma_slave_config slave_conf;
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enum dma_slave_buswidth addr_width;
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dma_addr_t usb_fifo_addr = (MUSB_FIFO_OFFSET(hw_ep->epnum) +
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ux500_channel->controller->phy_base);
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DBG(4, "packet_sz=%d, mode=%d, dma_addr=0x%x, len=%d is_tx=%d\n",
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packet_sz, mode, dma_addr, len, ux500_channel->is_tx);
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ux500_channel->cur_len = len;
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sg_init_table(&sg, 1);
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sg_set_page(&sg, pfn_to_page(PFN_DOWN(dma_addr)), len,
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offset_in_page(dma_addr));
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sg_dma_address(&sg) = dma_addr;
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sg_dma_len(&sg) = len;
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direction = ux500_channel->is_tx ? DMA_TO_DEVICE : DMA_FROM_DEVICE;
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addr_width = (len & 0x3) ? DMA_SLAVE_BUSWIDTH_1_BYTE :
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DMA_SLAVE_BUSWIDTH_4_BYTES;
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slave_conf.direction = direction;
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if (direction == DMA_FROM_DEVICE) {
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slave_conf.src_addr = usb_fifo_addr;
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slave_conf.src_addr_width = addr_width;
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slave_conf.src_maxburst = 16;
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} else {
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slave_conf.dst_addr = usb_fifo_addr;
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slave_conf.dst_addr_width = addr_width;
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slave_conf.dst_maxburst = 16;
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}
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dma_chan->device->device_control(dma_chan, DMA_SLAVE_CONFIG,
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(unsigned long) &slave_conf);
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dma_desc = dma_chan->device->
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device_prep_slave_sg(dma_chan, &sg, 1, direction,
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DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
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if (!dma_desc)
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return false;
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dma_desc->callback = ux500_dma_callback;
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dma_desc->callback_param = channel;
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ux500_channel->cookie = dma_desc->tx_submit(dma_desc);
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dma_async_issue_pending(dma_chan);
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return true;
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}
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static struct dma_channel *ux500_dma_channel_allocate(struct dma_controller *c,
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struct musb_hw_ep *hw_ep, u8 is_tx)
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{
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struct ux500_dma_controller *controller = container_of(c,
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struct ux500_dma_controller, controller);
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struct ux500_dma_channel *ux500_channel = NULL;
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u8 ch_num = hw_ep->epnum - 1;
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u32 max_ch;
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/* Max 8 DMA channels (0 - 7). Each DMA channel can only be allocated
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* to specified hw_ep. For example DMA channel 0 can only be allocated
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* to hw_ep 1 and 9.
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*/
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if (ch_num > 7)
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ch_num -= 8;
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max_ch = is_tx ? controller->num_tx_channels :
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controller->num_rx_channels;
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if (ch_num >= max_ch)
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return NULL;
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ux500_channel = is_tx ? &(controller->tx_channel[ch_num]) :
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&(controller->rx_channel[ch_num]) ;
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/* Check if channel is already used. */
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if (ux500_channel->is_allocated)
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return NULL;
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ux500_channel->hw_ep = hw_ep;
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ux500_channel->is_allocated = 1;
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DBG(7, "hw_ep=%d, is_tx=0x%x, channel=%d\n",
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hw_ep->epnum, is_tx, ch_num);
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return &(ux500_channel->channel);
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}
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static void ux500_dma_channel_release(struct dma_channel *channel)
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{
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struct ux500_dma_channel *ux500_channel = channel->private_data;
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DBG(7, "channel=%d\n", ux500_channel->ch_num);
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if (ux500_channel->is_allocated) {
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ux500_channel->is_allocated = 0;
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channel->status = MUSB_DMA_STATUS_FREE;
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channel->actual_len = 0;
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}
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}
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static int ux500_dma_is_compatible(struct dma_channel *channel,
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u16 maxpacket, void *buf, u32 length)
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{
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if ((maxpacket & 0x3) ||
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((int)buf & 0x3) ||
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(length < 512) ||
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(length & 0x3))
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return false;
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else
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return true;
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}
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static int ux500_dma_channel_program(struct dma_channel *channel,
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u16 packet_sz, u8 mode,
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dma_addr_t dma_addr, u32 len)
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{
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int ret;
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BUG_ON(channel->status == MUSB_DMA_STATUS_UNKNOWN ||
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channel->status == MUSB_DMA_STATUS_BUSY);
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if (!ux500_dma_is_compatible(channel, packet_sz, (void *)dma_addr, len))
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return false;
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channel->status = MUSB_DMA_STATUS_BUSY;
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channel->actual_len = 0;
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ret = ux500_configure_channel(channel, packet_sz, mode, dma_addr, len);
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if (!ret)
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channel->status = MUSB_DMA_STATUS_FREE;
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return ret;
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}
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static int ux500_dma_channel_abort(struct dma_channel *channel)
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{
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struct ux500_dma_channel *ux500_channel = channel->private_data;
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struct ux500_dma_controller *controller = ux500_channel->controller;
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struct musb *musb = controller->private_data;
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void __iomem *epio = musb->endpoints[ux500_channel->hw_ep->epnum].regs;
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u16 csr;
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DBG(4, "channel=%d, is_tx=%d\n", ux500_channel->ch_num,
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ux500_channel->is_tx);
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if (channel->status == MUSB_DMA_STATUS_BUSY) {
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if (ux500_channel->is_tx) {
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csr = musb_readw(epio, MUSB_TXCSR);
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csr &= ~(MUSB_TXCSR_AUTOSET |
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MUSB_TXCSR_DMAENAB |
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MUSB_TXCSR_DMAMODE);
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musb_writew(epio, MUSB_TXCSR, csr);
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} else {
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csr = musb_readw(epio, MUSB_RXCSR);
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csr &= ~(MUSB_RXCSR_AUTOCLEAR |
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MUSB_RXCSR_DMAENAB |
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MUSB_RXCSR_DMAMODE);
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musb_writew(epio, MUSB_RXCSR, csr);
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}
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ux500_channel->dma_chan->device->
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device_control(ux500_channel->dma_chan,
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DMA_TERMINATE_ALL, 0);
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channel->status = MUSB_DMA_STATUS_FREE;
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}
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return 0;
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}
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static int ux500_dma_controller_stop(struct dma_controller *c)
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{
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struct ux500_dma_controller *controller = container_of(c,
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struct ux500_dma_controller, controller);
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struct ux500_dma_channel *ux500_channel;
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struct dma_channel *channel;
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u8 ch_num;
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for (ch_num = 0; ch_num < controller->num_rx_channels; ch_num++) {
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channel = &controller->rx_channel[ch_num].channel;
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ux500_channel = channel->private_data;
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ux500_dma_channel_release(channel);
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if (ux500_channel->dma_chan)
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dma_release_channel(ux500_channel->dma_chan);
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}
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for (ch_num = 0; ch_num < controller->num_tx_channels; ch_num++) {
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channel = &controller->tx_channel[ch_num].channel;
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ux500_channel = channel->private_data;
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ux500_dma_channel_release(channel);
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if (ux500_channel->dma_chan)
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dma_release_channel(ux500_channel->dma_chan);
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}
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return 0;
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}
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static int ux500_dma_controller_start(struct dma_controller *c)
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{
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struct ux500_dma_controller *controller = container_of(c,
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struct ux500_dma_controller, controller);
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struct ux500_dma_channel *ux500_channel = NULL;
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struct musb *musb = controller->private_data;
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struct device *dev = musb->controller;
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struct musb_hdrc_platform_data *plat = dev->platform_data;
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struct ux500_musb_board_data *data = plat->board_data;
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struct dma_channel *dma_channel = NULL;
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u32 ch_num;
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u8 dir;
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u8 is_tx = 0;
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void **param_array;
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struct ux500_dma_channel *channel_array;
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u32 ch_count;
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void (*musb_channel_work)(struct work_struct *);
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dma_cap_mask_t mask;
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if ((data->num_rx_channels > UX500_MUSB_DMA_NUM_RX_CHANNELS) ||
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(data->num_tx_channels > UX500_MUSB_DMA_NUM_TX_CHANNELS))
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return -EINVAL;
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controller->num_rx_channels = data->num_rx_channels;
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controller->num_tx_channels = data->num_tx_channels;
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dma_cap_zero(mask);
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dma_cap_set(DMA_SLAVE, mask);
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/* Prepare the loop for RX channels */
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channel_array = controller->rx_channel;
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ch_count = data->num_rx_channels;
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param_array = data->dma_rx_param_array;
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musb_channel_work = ux500_rx_work;
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for (dir = 0; dir < 2; dir++) {
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for (ch_num = 0; ch_num < ch_count; ch_num++) {
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ux500_channel = &channel_array[ch_num];
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ux500_channel->controller = controller;
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ux500_channel->ch_num = ch_num;
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ux500_channel->is_tx = is_tx;
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dma_channel = &(ux500_channel->channel);
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dma_channel->private_data = ux500_channel;
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dma_channel->status = MUSB_DMA_STATUS_FREE;
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dma_channel->max_len = SZ_16M;
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ux500_channel->dma_chan = dma_request_channel(mask,
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data->dma_filter,
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param_array[ch_num]);
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if (!ux500_channel->dma_chan) {
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ERR("Dma pipe allocation error dir=%d ch=%d\n",
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dir, ch_num);
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/* Release already allocated channels */
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ux500_dma_controller_stop(c);
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return -EBUSY;
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}
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INIT_WORK(&ux500_channel->channel_work,
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musb_channel_work);
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}
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/* Prepare the loop for TX channels */
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channel_array = controller->tx_channel;
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ch_count = data->num_tx_channels;
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param_array = data->dma_tx_param_array;
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musb_channel_work = ux500_tx_work;
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is_tx = 1;
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}
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return 0;
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}
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void dma_controller_destroy(struct dma_controller *c)
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{
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struct ux500_dma_controller *controller = container_of(c,
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struct ux500_dma_controller, controller);
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kfree(controller);
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}
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struct dma_controller *__init
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dma_controller_create(struct musb *musb, void __iomem *base)
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{
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struct ux500_dma_controller *controller;
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struct platform_device *pdev = to_platform_device(musb->controller);
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struct resource *iomem;
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controller = kzalloc(sizeof(*controller), GFP_KERNEL);
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if (!controller)
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return NULL;
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controller->private_data = musb;
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/* Save physical address for DMA controller. */
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iomem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
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controller->phy_base = (dma_addr_t) iomem->start;
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controller->controller.start = ux500_dma_controller_start;
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controller->controller.stop = ux500_dma_controller_stop;
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controller->controller.channel_alloc = ux500_dma_channel_allocate;
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controller->controller.channel_release = ux500_dma_channel_release;
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controller->controller.channel_program = ux500_dma_channel_program;
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controller->controller.channel_abort = ux500_dma_channel_abort;
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controller->controller.is_compatible = ux500_dma_is_compatible;
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return &controller->controller;
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}
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