Merge tag 'v5.10-next-pm-domains-stable' into HEAD
This commit is contained in:
Matthias Brugger
commit
8d7d44f25c
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# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
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%YAML 1.2
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---
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$id: http://devicetree.org/schemas/power/mediatek,power-controller.yaml#
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$schema: http://devicetree.org/meta-schemas/core.yaml#
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title: Mediatek Power Domains Controller
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maintainers:
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- Weiyi Lu <weiyi.lu@mediatek.com>
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- Matthias Brugger <mbrugger@suse.com>
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description: |
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Mediatek processors include support for multiple power domains which can be
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powered up/down by software based on different application scenes to save power.
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IP cores belonging to a power domain should contain a 'power-domains'
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property that is a phandle for SCPSYS node representing the domain.
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properties:
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$nodename:
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const: power-controller
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compatible:
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enum:
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- mediatek,mt8173-power-controller
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- mediatek,mt8183-power-controller
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- mediatek,mt8192-power-controller
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'#power-domain-cells':
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const: 1
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'#address-cells':
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const: 1
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'#size-cells':
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const: 0
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patternProperties:
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"^power-domain@[0-9a-f]+$":
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type: object
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description: |
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Represents the power domains within the power controller node as documented
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in Documentation/devicetree/bindings/power/power-domain.yaml.
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properties:
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'#power-domain-cells':
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description:
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Must be 0 for nodes representing a single PM domain and 1 for nodes
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providing multiple PM domains.
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'#address-cells':
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const: 1
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'#size-cells':
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const: 0
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reg:
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description: |
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Power domain index. Valid values are defined in:
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"include/dt-bindings/power/mt8173-power.h" - for MT8173 type power domain.
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"include/dt-bindings/power/mt8183-power.h" - for MT8183 type power domain.
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"include/dt-bindings/power/mt8192-power.h" - for MT8192 type power domain.
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maxItems: 1
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clocks:
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description: |
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A number of phandles to clocks that need to be enabled during domain
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power-up sequencing.
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clock-names:
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description: |
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List of names of clocks, in order to match the power-up sequencing
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for each power domain we need to group the clocks by name. BASIC
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clocks need to be enabled before enabling the corresponding power
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domain, and should not have a '-' in their name (i.e mm, mfg, venc).
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SUSBYS clocks need to be enabled before releasing the bus protection,
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and should contain a '-' in their name (i.e mm-0, isp-0, cam-0).
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In order to follow properly the power-up sequencing, the clocks must
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be specified by order, adding first the BASIC clocks followed by the
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SUSBSYS clocks.
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mediatek,infracfg:
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$ref: /schemas/types.yaml#definitions/phandle
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description: phandle to the device containing the INFRACFG register range.
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mediatek,smi:
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$ref: /schemas/types.yaml#definitions/phandle
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description: phandle to the device containing the SMI register range.
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patternProperties:
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"^power-domain@[0-9a-f]+$":
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type: object
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description: |
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Represents a power domain child within a power domain parent node.
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properties:
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'#power-domain-cells':
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description:
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Must be 0 for nodes representing a single PM domain and 1 for nodes
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providing multiple PM domains.
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'#address-cells':
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const: 1
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'#size-cells':
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const: 0
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reg:
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maxItems: 1
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clocks:
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description: |
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A number of phandles to clocks that need to be enabled during domain
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power-up sequencing.
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clock-names:
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description: |
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List of names of clocks, in order to match the power-up sequencing
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for each power domain we need to group the clocks by name. BASIC
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clocks need to be enabled before enabling the corresponding power
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domain, and should not have a '-' in their name (i.e mm, mfg, venc).
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SUSBYS clocks need to be enabled before releasing the bus protection,
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and should contain a '-' in their name (i.e mm-0, isp-0, cam-0).
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In order to follow properly the power-up sequencing, the clocks must
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be specified by order, adding first the BASIC clocks followed by the
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SUSBSYS clocks.
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mediatek,infracfg:
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$ref: /schemas/types.yaml#definitions/phandle
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description: phandle to the device containing the INFRACFG register range.
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mediatek,smi:
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$ref: /schemas/types.yaml#definitions/phandle
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description: phandle to the device containing the SMI register range.
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patternProperties:
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"^power-domain@[0-9a-f]+$":
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type: object
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description: |
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Represents a power domain child within a power domain parent node.
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properties:
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'#power-domain-cells':
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description:
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Must be 0 for nodes representing a single PM domain and 1 for nodes
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providing multiple PM domains.
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'#address-cells':
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const: 1
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'#size-cells':
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const: 0
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reg:
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maxItems: 1
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clocks:
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description: |
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A number of phandles to clocks that need to be enabled during domain
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power-up sequencing.
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clock-names:
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description: |
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List of names of clocks, in order to match the power-up sequencing
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for each power domain we need to group the clocks by name. BASIC
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clocks need to be enabled before enabling the corresponding power
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domain, and should not have a '-' in their name (i.e mm, mfg, venc).
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SUSBYS clocks need to be enabled before releasing the bus protection,
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and should contain a '-' in their name (i.e mm-0, isp-0, cam-0).
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In order to follow properly the power-up sequencing, the clocks must
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be specified by order, adding first the BASIC clocks followed by the
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SUSBSYS clocks.
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mediatek,infracfg:
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$ref: /schemas/types.yaml#definitions/phandle
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description: phandle to the device containing the INFRACFG register range.
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mediatek,smi:
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$ref: /schemas/types.yaml#definitions/phandle
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description: phandle to the device containing the SMI register range.
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required:
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- reg
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additionalProperties: false
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required:
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- reg
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additionalProperties: false
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required:
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- reg
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additionalProperties: false
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required:
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- compatible
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additionalProperties: false
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examples:
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- |
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#include <dt-bindings/clock/mt8173-clk.h>
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#include <dt-bindings/power/mt8173-power.h>
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soc {
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#address-cells = <2>;
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#size-cells = <2>;
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scpsys: syscon@10006000 {
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compatible = "syscon", "simple-mfd";
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reg = <0 0x10006000 0 0x1000>;
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spm: power-controller {
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compatible = "mediatek,mt8173-power-controller";
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#address-cells = <1>;
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#size-cells = <0>;
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#power-domain-cells = <1>;
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/* power domains of the SoC */
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power-domain@MT8173_POWER_DOMAIN_VDEC {
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reg = <MT8173_POWER_DOMAIN_VDEC>;
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clocks = <&topckgen CLK_TOP_MM_SEL>;
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clock-names = "mm";
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#power-domain-cells = <0>;
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};
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power-domain@MT8173_POWER_DOMAIN_VENC {
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reg = <MT8173_POWER_DOMAIN_VENC>;
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clocks = <&topckgen CLK_TOP_MM_SEL>,
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<&topckgen CLK_TOP_VENC_SEL>;
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clock-names = "mm", "venc";
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#power-domain-cells = <0>;
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};
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power-domain@MT8173_POWER_DOMAIN_ISP {
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reg = <MT8173_POWER_DOMAIN_ISP>;
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clocks = <&topckgen CLK_TOP_MM_SEL>;
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clock-names = "mm";
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#power-domain-cells = <0>;
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};
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power-domain@MT8173_POWER_DOMAIN_MM {
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reg = <MT8173_POWER_DOMAIN_MM>;
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clocks = <&topckgen CLK_TOP_MM_SEL>;
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clock-names = "mm";
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#power-domain-cells = <0>;
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mediatek,infracfg = <&infracfg>;
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};
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power-domain@MT8173_POWER_DOMAIN_VENC_LT {
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reg = <MT8173_POWER_DOMAIN_VENC_LT>;
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clocks = <&topckgen CLK_TOP_MM_SEL>,
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<&topckgen CLK_TOP_VENC_LT_SEL>;
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clock-names = "mm", "venclt";
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#power-domain-cells = <0>;
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};
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power-domain@MT8173_POWER_DOMAIN_AUDIO {
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reg = <MT8173_POWER_DOMAIN_AUDIO>;
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#power-domain-cells = <0>;
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};
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power-domain@MT8173_POWER_DOMAIN_USB {
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reg = <MT8173_POWER_DOMAIN_USB>;
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#power-domain-cells = <0>;
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};
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power-domain@MT8173_POWER_DOMAIN_MFG_ASYNC {
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reg = <MT8173_POWER_DOMAIN_MFG_ASYNC>;
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clocks = <&clk26m>;
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clock-names = "mfg";
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#address-cells = <1>;
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#size-cells = <0>;
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#power-domain-cells = <1>;
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power-domain@MT8173_POWER_DOMAIN_MFG_2D {
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reg = <MT8173_POWER_DOMAIN_MFG_2D>;
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#address-cells = <1>;
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#size-cells = <0>;
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#power-domain-cells = <1>;
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power-domain@MT8173_POWER_DOMAIN_MFG {
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reg = <MT8173_POWER_DOMAIN_MFG>;
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#power-domain-cells = <0>;
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mediatek,infracfg = <&infracfg>;
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};
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};
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};
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};
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};
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};
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@ -0,0 +1,26 @@
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/* SPDX-License-Identifier: GPL-2.0 */
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/*
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* Copyright (c) 2020 MediaTek Inc.
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* Author: Weiyi Lu <weiyi.lu@mediatek.com>
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*/
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#ifndef _DT_BINDINGS_POWER_MT8183_POWER_H
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#define _DT_BINDINGS_POWER_MT8183_POWER_H
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#define MT8183_POWER_DOMAIN_AUDIO 0
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#define MT8183_POWER_DOMAIN_CONN 1
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#define MT8183_POWER_DOMAIN_MFG_ASYNC 2
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#define MT8183_POWER_DOMAIN_MFG 3
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#define MT8183_POWER_DOMAIN_MFG_CORE0 4
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#define MT8183_POWER_DOMAIN_MFG_CORE1 5
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#define MT8183_POWER_DOMAIN_MFG_2D 6
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#define MT8183_POWER_DOMAIN_DISP 7
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#define MT8183_POWER_DOMAIN_CAM 8
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#define MT8183_POWER_DOMAIN_ISP 9
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#define MT8183_POWER_DOMAIN_VDEC 10
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#define MT8183_POWER_DOMAIN_VENC 11
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#define MT8183_POWER_DOMAIN_VPU_TOP 12
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#define MT8183_POWER_DOMAIN_VPU_CORE0 13
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#define MT8183_POWER_DOMAIN_VPU_CORE1 14
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#endif /* _DT_BINDINGS_POWER_MT8183_POWER_H */
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@ -0,0 +1,32 @@
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/* SPDX-License-Identifier: GPL-2.0
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*
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* Copyright (c) 2020 MediaTek Inc.
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* Author: Weiyi Lu <weiyi.lu@mediatek.com>
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*/
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#ifndef _DT_BINDINGS_POWER_MT8192_POWER_H
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#define _DT_BINDINGS_POWER_MT8192_POWER_H
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#define MT8192_POWER_DOMAIN_AUDIO 0
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#define MT8192_POWER_DOMAIN_CONN 1
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#define MT8192_POWER_DOMAIN_MFG0 2
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#define MT8192_POWER_DOMAIN_MFG1 3
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#define MT8192_POWER_DOMAIN_MFG2 4
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#define MT8192_POWER_DOMAIN_MFG3 5
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#define MT8192_POWER_DOMAIN_MFG4 6
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#define MT8192_POWER_DOMAIN_MFG5 7
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#define MT8192_POWER_DOMAIN_MFG6 8
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#define MT8192_POWER_DOMAIN_DISP 9
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#define MT8192_POWER_DOMAIN_IPE 10
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#define MT8192_POWER_DOMAIN_ISP 11
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#define MT8192_POWER_DOMAIN_ISP2 12
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#define MT8192_POWER_DOMAIN_MDP 13
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#define MT8192_POWER_DOMAIN_VENC 14
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#define MT8192_POWER_DOMAIN_VDEC 15
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#define MT8192_POWER_DOMAIN_VDEC2 16
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#define MT8192_POWER_DOMAIN_CAM 17
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#define MT8192_POWER_DOMAIN_CAM_RAWA 18
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#define MT8192_POWER_DOMAIN_CAM_RAWB 19
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#define MT8192_POWER_DOMAIN_CAM_RAWC 20
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#endif /* _DT_BINDINGS_POWER_MT8192_POWER_H */
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