drm/amdgpu: update the method to get fb_loc of memory training(V4)
The method of getting fb_loc changed from parsing VBIOS to taking certain offset from top of VRAM Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Tianci.Yin <tianci.yin@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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@ -636,9 +636,8 @@ struct amdgpu_fw_vram_usage {
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struct amdgpu_bo *reserved_bo;
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void *va;
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/* Offset on the top of VRAM, used as c2p write buffer.
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/* GDDR6 training support flag.
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*/
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u64 mem_train_fb_loc;
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bool mem_train_support;
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};
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@ -2022,7 +2022,7 @@ int amdgpu_atombios_init(struct amdgpu_device *adev)
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if (adev->is_atom_fw) {
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amdgpu_atomfirmware_scratch_regs_init(adev);
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amdgpu_atomfirmware_allocate_fb_scratch(adev);
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ret = amdgpu_atomfirmware_get_mem_train_fb_loc(adev);
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ret = amdgpu_atomfirmware_get_mem_train_info(adev);
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if (ret) {
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DRM_ERROR("Failed to get mem train fb location.\n");
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return ret;
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@ -525,16 +525,12 @@ static int gddr6_mem_train_support(struct amdgpu_device *adev)
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return ret;
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}
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int amdgpu_atomfirmware_get_mem_train_fb_loc(struct amdgpu_device *adev)
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int amdgpu_atomfirmware_get_mem_train_info(struct amdgpu_device *adev)
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{
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struct atom_context *ctx = adev->mode_info.atom_context;
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unsigned char *bios = ctx->bios;
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struct vram_reserve_block *reserved_block;
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int index, block_number;
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int index;
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uint8_t frev, crev;
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uint16_t data_offset, size;
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uint32_t start_address_in_kb;
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uint64_t offset;
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int ret;
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adev->fw_vram_usage.mem_train_support = false;
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@ -569,32 +565,6 @@ int amdgpu_atomfirmware_get_mem_train_fb_loc(struct amdgpu_device *adev)
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return -EINVAL;
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}
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reserved_block = (struct vram_reserve_block *)
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(bios + data_offset + sizeof(struct atom_common_table_header));
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block_number = ((unsigned int)size - sizeof(struct atom_common_table_header))
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/ sizeof(struct vram_reserve_block);
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reserved_block += (block_number > 0) ? block_number-1 : 0;
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DRM_DEBUG("block_number:0x%04x, last block: 0x%08xkb sz, %dkb fw, %dkb drv.\n",
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block_number,
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le32_to_cpu(reserved_block->start_address_in_kb),
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le16_to_cpu(reserved_block->used_by_firmware_in_kb),
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le16_to_cpu(reserved_block->used_by_driver_in_kb));
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if (reserved_block->used_by_firmware_in_kb > 0) {
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start_address_in_kb = le32_to_cpu(reserved_block->start_address_in_kb);
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offset = (uint64_t)start_address_in_kb * ONE_KiB;
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if ((offset & (ONE_MiB - 1)) < (4 * ONE_KiB + 1) ) {
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offset -= ONE_MiB;
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}
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offset &= ~(ONE_MiB - 1);
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adev->fw_vram_usage.mem_train_fb_loc = offset;
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adev->fw_vram_usage.mem_train_support = true;
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DRM_DEBUG("mem_train_fb_loc:0x%09llx.\n", offset);
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ret = 0;
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} else {
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DRM_ERROR("used_by_firmware_in_kb is 0!\n");
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ret = -EINVAL;
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}
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return ret;
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adev->fw_vram_usage.mem_train_support = true;
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return 0;
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}
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@ -31,7 +31,7 @@ void amdgpu_atomfirmware_scratch_regs_init(struct amdgpu_device *adev);
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int amdgpu_atomfirmware_allocate_fb_scratch(struct amdgpu_device *adev);
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int amdgpu_atomfirmware_get_vram_info(struct amdgpu_device *adev,
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int *vram_width, int *vram_type, int *vram_vendor);
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int amdgpu_atomfirmware_get_mem_train_fb_loc(struct amdgpu_device *adev);
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int amdgpu_atomfirmware_get_mem_train_info(struct amdgpu_device *adev);
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int amdgpu_atomfirmware_get_clock_info(struct amdgpu_device *adev);
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int amdgpu_atomfirmware_get_gfx_info(struct amdgpu_device *adev);
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bool amdgpu_atomfirmware_mem_ecc_supported(struct amdgpu_device *adev);
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@ -1720,6 +1720,14 @@ static int amdgpu_ttm_training_reserve_vram_fini(struct amdgpu_device *adev)
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return 0;
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}
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static u64 amdgpu_ttm_training_get_c2p_offset(u64 vram_size)
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{
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if ((vram_size & (ONE_MiB - 1)) < (4 * ONE_KiB + 1) )
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vram_size -= ONE_MiB;
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return ALIGN(vram_size, ONE_MiB);
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}
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/**
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* amdgpu_ttm_training_reserve_vram_init - create bo vram reservation from memory training
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*
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@ -1738,7 +1746,7 @@ static int amdgpu_ttm_training_reserve_vram_init(struct amdgpu_device *adev)
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return 0;
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}
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ctx->c2p_train_data_offset = adev->fw_vram_usage.mem_train_fb_loc;
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ctx->c2p_train_data_offset = amdgpu_ttm_training_get_c2p_offset(adev->gmc.mc_vram_size);
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ctx->p2c_train_data_offset = (adev->gmc.mc_vram_size - GDDR6_MEM_TRAINING_OFFSET);
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ctx->train_data_size = GDDR6_MEM_TRAINING_DATA_SIZE_IN_BYTES;
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@ -66,6 +66,13 @@ struct amdgpu_copy_mem {
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unsigned long offset;
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};
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/* Definitions for constance */
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enum amdgpu_internal_constants
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{
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ONE_KiB = 0x400,
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ONE_MiB = 0x100000,
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};
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extern const struct ttm_mem_type_manager_func amdgpu_gtt_mgr_func;
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extern const struct ttm_mem_type_manager_func amdgpu_vram_mgr_func;
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@ -672,20 +672,6 @@ struct vram_usagebyfirmware_v2_1
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uint16_t used_by_driver_in_kb;
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};
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/* This is part of vram_usagebyfirmware_v2_1 */
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struct vram_reserve_block
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{
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uint32_t start_address_in_kb;
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uint16_t used_by_firmware_in_kb;
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uint16_t used_by_driver_in_kb;
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};
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/* Definitions for constance */
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enum atomfirmware_internal_constants
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{
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ONE_KiB = 0x400,
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ONE_MiB = 0x100000,
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};
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/*
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***************************************************************************
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