Merge branch 'pci/enumeration'
- If user prevents VF probing, return error instead of pretending a driver has claimed the VF (Alex Williamson) - Always allow probing with driver_override (Alex Williamson) - Decode PCIe 32 GT/s link speed (Gustavo Pimentel) - Ignore lockdep for sysfs remove to avoid lockdep false positive (Marek Vasut) * pci/enumeration: PCI: sysfs: Ignore lockdep for remove attribute PCI: Decode PCIe 32 GT/s link speed PCI: Always allow probing with driver_override PCI: Return error if cannot probe VF
This commit is contained in:
commit
8cf80c5c14
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@ -399,7 +399,8 @@ void __weak pcibios_free_irq(struct pci_dev *dev)
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#ifdef CONFIG_PCI_IOV
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static inline bool pci_device_can_probe(struct pci_dev *pdev)
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{
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return (!pdev->is_virtfn || pdev->physfn->sriov->drivers_autoprobe);
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return (!pdev->is_virtfn || pdev->physfn->sriov->drivers_autoprobe ||
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pdev->driver_override);
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}
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#else
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static inline bool pci_device_can_probe(struct pci_dev *pdev)
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@ -414,6 +415,9 @@ static int pci_device_probe(struct device *dev)
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struct pci_dev *pci_dev = to_pci_dev(dev);
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struct pci_driver *drv = to_pci_driver(dev->driver);
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if (!pci_device_can_probe(pci_dev))
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return -ENODEV;
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pci_assign_irq(pci_dev);
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error = pcibios_alloc_irq(pci_dev);
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@ -421,12 +425,10 @@ static int pci_device_probe(struct device *dev)
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return error;
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pci_dev_get(pci_dev);
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if (pci_device_can_probe(pci_dev)) {
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error = __pci_device_probe(drv, pci_dev);
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if (error) {
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pcibios_free_irq(pci_dev);
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pci_dev_put(pci_dev);
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}
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error = __pci_device_probe(drv, pci_dev);
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if (error) {
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pcibios_free_irq(pci_dev);
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pci_dev_put(pci_dev);
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}
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return error;
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@ -182,6 +182,9 @@ static ssize_t current_link_speed_show(struct device *dev,
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return -EINVAL;
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switch (linkstat & PCI_EXP_LNKSTA_CLS) {
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case PCI_EXP_LNKSTA_CLS_32_0GB:
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speed = "32 GT/s";
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break;
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case PCI_EXP_LNKSTA_CLS_16_0GB:
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speed = "16 GT/s";
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break;
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@ -477,7 +480,7 @@ static ssize_t remove_store(struct device *dev, struct device_attribute *attr,
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pci_stop_and_remove_bus_device_locked(to_pci_dev(dev));
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return count;
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}
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static struct device_attribute dev_remove_attr = __ATTR(remove,
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static struct device_attribute dev_remove_attr = __ATTR_IGNORE_LOCKDEP(remove,
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(S_IWUSR|S_IWGRP),
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NULL, remove_store);
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@ -5621,7 +5621,9 @@ enum pci_bus_speed pcie_get_speed_cap(struct pci_dev *dev)
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*/
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pcie_capability_read_dword(dev, PCI_EXP_LNKCAP2, &lnkcap2);
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if (lnkcap2) { /* PCIe r3.0-compliant */
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if (lnkcap2 & PCI_EXP_LNKCAP2_SLS_16_0GB)
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if (lnkcap2 & PCI_EXP_LNKCAP2_SLS_32_0GB)
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return PCIE_SPEED_32_0GT;
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else if (lnkcap2 & PCI_EXP_LNKCAP2_SLS_16_0GB)
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return PCIE_SPEED_16_0GT;
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else if (lnkcap2 & PCI_EXP_LNKCAP2_SLS_8_0GB)
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return PCIE_SPEED_8_0GT;
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@ -668,7 +668,7 @@ const unsigned char pcie_link_speed[] = {
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PCIE_SPEED_5_0GT, /* 2 */
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PCIE_SPEED_8_0GT, /* 3 */
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PCIE_SPEED_16_0GT, /* 4 */
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PCI_SPEED_UNKNOWN, /* 5 */
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PCIE_SPEED_32_0GT, /* 5 */
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PCI_SPEED_UNKNOWN, /* 6 */
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PCI_SPEED_UNKNOWN, /* 7 */
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PCI_SPEED_UNKNOWN, /* 8 */
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@ -75,6 +75,7 @@ static const char *pci_bus_speed_strings[] = {
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"5.0 GT/s PCIe", /* 0x15 */
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"8.0 GT/s PCIe", /* 0x16 */
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"16.0 GT/s PCIe", /* 0x17 */
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"32.0 GT/s PCIe", /* 0x18 */
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};
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static ssize_t bus_speed_read(enum pci_bus_speed speed, char *buf)
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@ -260,6 +260,7 @@ enum pci_bus_speed {
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PCIE_SPEED_5_0GT = 0x15,
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PCIE_SPEED_8_0GT = 0x16,
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PCIE_SPEED_16_0GT = 0x17,
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PCIE_SPEED_32_0GT = 0x18,
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PCI_SPEED_UNKNOWN = 0xff,
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};
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@ -528,6 +528,7 @@
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#define PCI_EXP_LNKCAP_SLS_5_0GB 0x00000002 /* LNKCAP2 SLS Vector bit 1 */
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#define PCI_EXP_LNKCAP_SLS_8_0GB 0x00000003 /* LNKCAP2 SLS Vector bit 2 */
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#define PCI_EXP_LNKCAP_SLS_16_0GB 0x00000004 /* LNKCAP2 SLS Vector bit 3 */
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#define PCI_EXP_LNKCAP_SLS_32_0GB 0x00000005 /* LNKCAP2 SLS Vector bit 4 */
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#define PCI_EXP_LNKCAP_MLW 0x000003f0 /* Maximum Link Width */
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#define PCI_EXP_LNKCAP_ASPMS 0x00000c00 /* ASPM Support */
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#define PCI_EXP_LNKCAP_L0SEL 0x00007000 /* L0s Exit Latency */
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@ -556,6 +557,7 @@
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#define PCI_EXP_LNKSTA_CLS_5_0GB 0x0002 /* Current Link Speed 5.0GT/s */
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#define PCI_EXP_LNKSTA_CLS_8_0GB 0x0003 /* Current Link Speed 8.0GT/s */
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#define PCI_EXP_LNKSTA_CLS_16_0GB 0x0004 /* Current Link Speed 16.0GT/s */
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#define PCI_EXP_LNKSTA_CLS_32_0GB 0x0005 /* Current Link Speed 32.0GT/s */
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#define PCI_EXP_LNKSTA_NLW 0x03f0 /* Negotiated Link Width */
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#define PCI_EXP_LNKSTA_NLW_X1 0x0010 /* Current Link Width x1 */
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#define PCI_EXP_LNKSTA_NLW_X2 0x0020 /* Current Link Width x2 */
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@ -661,6 +663,7 @@
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#define PCI_EXP_LNKCAP2_SLS_5_0GB 0x00000004 /* Supported Speed 5GT/s */
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#define PCI_EXP_LNKCAP2_SLS_8_0GB 0x00000008 /* Supported Speed 8GT/s */
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#define PCI_EXP_LNKCAP2_SLS_16_0GB 0x00000010 /* Supported Speed 16GT/s */
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#define PCI_EXP_LNKCAP2_SLS_32_0GB 0x00000020 /* Supported Speed 32GT/s */
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#define PCI_EXP_LNKCAP2_CROSSLINK 0x00000100 /* Crosslink supported */
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#define PCI_EXP_LNKCTL2 48 /* Link Control 2 */
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#define PCI_EXP_LNKCTL2_TLS 0x000f
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@ -668,6 +671,7 @@
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#define PCI_EXP_LNKCTL2_TLS_5_0GT 0x0002 /* Supported Speed 5GT/s */
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#define PCI_EXP_LNKCTL2_TLS_8_0GT 0x0003 /* Supported Speed 8GT/s */
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#define PCI_EXP_LNKCTL2_TLS_16_0GT 0x0004 /* Supported Speed 16GT/s */
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#define PCI_EXP_LNKCTL2_TLS_32_0GT 0x0005 /* Supported Speed 32GT/s */
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#define PCI_EXP_LNKSTA2 50 /* Link Status 2 */
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#define PCI_CAP_EXP_ENDPOINT_SIZEOF_V2 52 /* v2 endpoints with link end here */
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#define PCI_EXP_SLTCAP2 52 /* Slot Capabilities 2 */
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