fjes: Hardware initialization routine
This patch adds hardware initialization routine to be invoked at driver's .probe routine. Signed-off-by: Taku Izumi <izumi.taku@jp.fujitsu.com> Signed-off-by: David S. Miller <davem@davemloft.net>
This commit is contained in:
Taku Izumi
David S. Miller
parent
658d439b22
commit
8cdc3f6c5d
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@ -27,4 +27,4 @@
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obj-$(CONFIG_FUJITSU_ES) += fjes.o
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fjes-objs := fjes_main.o
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fjes-objs := fjes_main.o fjes_hw.o
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@ -28,5 +28,6 @@
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extern char fjes_driver_name[];
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extern char fjes_driver_version[];
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extern const u32 fjes_support_mtu[];
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#endif /* FJES_H_ */
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@ -0,0 +1,295 @@
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/*
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* FUJITSU Extended Socket Network Device driver
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* Copyright (c) 2015 FUJITSU LIMITED
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms and conditions of the GNU General Public License,
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* version 2, as published by the Free Software Foundation.
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*
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* This program is distributed in the hope it will be useful, but WITHOUT
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* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
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* more details.
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*
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* You should have received a copy of the GNU General Public License along with
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* this program; if not, see <http://www.gnu.org/licenses/>.
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*
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* The full GNU General Public License is included in this distribution in
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* the file called "COPYING".
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*
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*/
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#include "fjes_hw.h"
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#include "fjes.h"
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/* supported MTU list */
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const u32 fjes_support_mtu[] = {
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FJES_MTU_DEFINE(8 * 1024),
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FJES_MTU_DEFINE(16 * 1024),
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FJES_MTU_DEFINE(32 * 1024),
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FJES_MTU_DEFINE(64 * 1024),
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0
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};
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u32 fjes_hw_rd32(struct fjes_hw *hw, u32 reg)
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{
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u8 *base = hw->base;
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u32 value = 0;
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value = readl(&base[reg]);
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return value;
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}
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static u8 *fjes_hw_iomap(struct fjes_hw *hw)
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{
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u8 *base;
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if (!request_mem_region(hw->hw_res.start, hw->hw_res.size,
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fjes_driver_name)) {
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pr_err("request_mem_region failed\n");
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return NULL;
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}
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base = (u8 *)ioremap_nocache(hw->hw_res.start, hw->hw_res.size);
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return base;
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}
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int fjes_hw_reset(struct fjes_hw *hw)
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{
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union REG_DCTL dctl;
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int timeout;
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dctl.reg = 0;
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dctl.bits.reset = 1;
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wr32(XSCT_DCTL, dctl.reg);
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timeout = FJES_DEVICE_RESET_TIMEOUT * 1000;
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dctl.reg = rd32(XSCT_DCTL);
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while ((dctl.bits.reset == 1) && (timeout > 0)) {
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msleep(1000);
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dctl.reg = rd32(XSCT_DCTL);
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timeout -= 1000;
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}
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return timeout > 0 ? 0 : -EIO;
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}
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static int fjes_hw_get_max_epid(struct fjes_hw *hw)
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{
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union REG_MAX_EP info;
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info.reg = rd32(XSCT_MAX_EP);
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return info.bits.maxep;
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}
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static int fjes_hw_get_my_epid(struct fjes_hw *hw)
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{
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union REG_OWNER_EPID info;
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info.reg = rd32(XSCT_OWNER_EPID);
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return info.bits.epid;
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}
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static int fjes_hw_alloc_shared_status_region(struct fjes_hw *hw)
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{
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size_t size;
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size = sizeof(struct fjes_device_shared_info) +
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(sizeof(u8) * hw->max_epid);
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hw->hw_info.share = kzalloc(size, GFP_KERNEL);
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if (!hw->hw_info.share)
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return -ENOMEM;
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hw->hw_info.share->epnum = hw->max_epid;
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return 0;
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}
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static int fjes_hw_alloc_epbuf(struct epbuf_handler *epbh)
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{
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void *mem;
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mem = vzalloc(EP_BUFFER_SIZE);
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if (!mem)
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return -ENOMEM;
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epbh->buffer = mem;
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epbh->size = EP_BUFFER_SIZE;
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epbh->info = (union ep_buffer_info *)mem;
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epbh->ring = (u8 *)(mem + sizeof(union ep_buffer_info));
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return 0;
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}
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void fjes_hw_setup_epbuf(struct epbuf_handler *epbh, u8 *mac_addr, u32 mtu)
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{
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union ep_buffer_info *info = epbh->info;
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u16 vlan_id[EP_BUFFER_SUPPORT_VLAN_MAX];
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int i;
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for (i = 0; i < EP_BUFFER_SUPPORT_VLAN_MAX; i++)
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vlan_id[i] = info->v1i.vlan_id[i];
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memset(info, 0, sizeof(union ep_buffer_info));
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info->v1i.version = 0; /* version 0 */
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for (i = 0; i < ETH_ALEN; i++)
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info->v1i.mac_addr[i] = mac_addr[i];
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info->v1i.head = 0;
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info->v1i.tail = 1;
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info->v1i.info_size = sizeof(union ep_buffer_info);
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info->v1i.buffer_size = epbh->size - info->v1i.info_size;
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info->v1i.frame_max = FJES_MTU_TO_FRAME_SIZE(mtu);
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info->v1i.count_max =
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EP_RING_NUM(info->v1i.buffer_size, info->v1i.frame_max);
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for (i = 0; i < EP_BUFFER_SUPPORT_VLAN_MAX; i++)
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info->v1i.vlan_id[i] = vlan_id[i];
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}
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void
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fjes_hw_init_command_registers(struct fjes_hw *hw,
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struct fjes_device_command_param *param)
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{
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/* Request Buffer length */
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wr32(XSCT_REQBL, (__le32)(param->req_len));
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/* Response Buffer Length */
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wr32(XSCT_RESPBL, (__le32)(param->res_len));
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/* Request Buffer Address */
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wr32(XSCT_REQBAL,
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(__le32)(param->req_start & GENMASK_ULL(31, 0)));
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wr32(XSCT_REQBAH,
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(__le32)((param->req_start & GENMASK_ULL(63, 32)) >> 32));
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/* Response Buffer Address */
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wr32(XSCT_RESPBAL,
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(__le32)(param->res_start & GENMASK_ULL(31, 0)));
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wr32(XSCT_RESPBAH,
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(__le32)((param->res_start & GENMASK_ULL(63, 32)) >> 32));
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/* Share status address */
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wr32(XSCT_SHSTSAL,
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(__le32)(param->share_start & GENMASK_ULL(31, 0)));
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wr32(XSCT_SHSTSAH,
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(__le32)((param->share_start & GENMASK_ULL(63, 32)) >> 32));
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}
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static int fjes_hw_setup(struct fjes_hw *hw)
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{
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u8 mac[ETH_ALEN] = { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 };
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struct fjes_device_command_param param;
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struct ep_share_mem_info *buf_pair;
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size_t mem_size;
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int result;
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int epidx;
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void *buf;
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hw->hw_info.max_epid = &hw->max_epid;
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hw->hw_info.my_epid = &hw->my_epid;
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buf = kcalloc(hw->max_epid, sizeof(struct ep_share_mem_info),
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GFP_KERNEL);
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if (!buf)
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return -ENOMEM;
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hw->ep_shm_info = (struct ep_share_mem_info *)buf;
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mem_size = FJES_DEV_REQ_BUF_SIZE(hw->max_epid);
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hw->hw_info.req_buf = kzalloc(mem_size, GFP_KERNEL);
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if (!(hw->hw_info.req_buf))
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return -ENOMEM;
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hw->hw_info.req_buf_size = mem_size;
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mem_size = FJES_DEV_RES_BUF_SIZE(hw->max_epid);
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hw->hw_info.res_buf = kzalloc(mem_size, GFP_KERNEL);
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if (!(hw->hw_info.res_buf))
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return -ENOMEM;
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hw->hw_info.res_buf_size = mem_size;
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result = fjes_hw_alloc_shared_status_region(hw);
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if (result)
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return result;
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hw->hw_info.buffer_share_bit = 0;
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hw->hw_info.buffer_unshare_reserve_bit = 0;
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for (epidx = 0; epidx < hw->max_epid; epidx++) {
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if (epidx != hw->my_epid) {
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buf_pair = &hw->ep_shm_info[epidx];
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result = fjes_hw_alloc_epbuf(&buf_pair->tx);
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if (result)
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return result;
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result = fjes_hw_alloc_epbuf(&buf_pair->rx);
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if (result)
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return result;
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fjes_hw_setup_epbuf(&buf_pair->tx, mac,
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fjes_support_mtu[0]);
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fjes_hw_setup_epbuf(&buf_pair->rx, mac,
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fjes_support_mtu[0]);
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}
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}
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memset(¶m, 0, sizeof(param));
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param.req_len = hw->hw_info.req_buf_size;
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param.req_start = __pa(hw->hw_info.req_buf);
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param.res_len = hw->hw_info.res_buf_size;
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param.res_start = __pa(hw->hw_info.res_buf);
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param.share_start = __pa(hw->hw_info.share->ep_status);
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fjes_hw_init_command_registers(hw, ¶m);
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return 0;
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}
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int fjes_hw_init(struct fjes_hw *hw)
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{
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int ret;
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hw->base = fjes_hw_iomap(hw);
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if (!hw->base)
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return -EIO;
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ret = fjes_hw_reset(hw);
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if (ret)
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return ret;
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fjes_hw_set_irqmask(hw, REG_ICTL_MASK_ALL, true);
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mutex_init(&hw->hw_info.lock);
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hw->max_epid = fjes_hw_get_max_epid(hw);
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hw->my_epid = fjes_hw_get_my_epid(hw);
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if ((hw->max_epid == 0) || (hw->my_epid >= hw->max_epid))
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return -ENXIO;
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ret = fjes_hw_setup(hw);
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return ret;
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}
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void fjes_hw_set_irqmask(struct fjes_hw *hw,
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enum REG_ICTL_MASK intr_mask, bool mask)
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{
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if (mask)
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wr32(XSCT_IMS, intr_mask);
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else
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wr32(XSCT_IMC, intr_mask);
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}
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@ -0,0 +1,251 @@
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/*
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* FUJITSU Extended Socket Network Device driver
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* Copyright (c) 2015 FUJITSU LIMITED
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms and conditions of the GNU General Public License,
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* version 2, as published by the Free Software Foundation.
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*
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* This program is distributed in the hope it will be useful, but WITHOUT
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* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
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* more details.
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*
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* You should have received a copy of the GNU General Public License along with
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* this program; if not, see <http://www.gnu.org/licenses/>.
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*
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* The full GNU General Public License is included in this distribution in
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* the file called "COPYING".
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*
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*/
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#ifndef FJES_HW_H_
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#define FJES_HW_H_
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#include <linux/netdevice.h>
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#include <linux/if_vlan.h>
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#include <linux/vmalloc.h>
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#include "fjes_regs.h"
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struct fjes_hw;
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#define EP_BUFFER_SUPPORT_VLAN_MAX 4
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#define EP_BUFFER_INFO_SIZE 4096
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#define FJES_DEVICE_RESET_TIMEOUT ((17 + 1) * 3) /* sec */
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#define EP_BUFFER_SIZE \
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(((sizeof(union ep_buffer_info) + (128 * (64 * 1024))) \
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/ EP_BUFFER_INFO_SIZE) * EP_BUFFER_INFO_SIZE)
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#define EP_RING_NUM(buffer_size, frame_size) \
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(u32)((buffer_size) / (frame_size))
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#define FJES_MTU_TO_BUFFER_SIZE(mtu) \
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(ETH_HLEN + VLAN_HLEN + (mtu) + ETH_FCS_LEN)
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#define FJES_MTU_TO_FRAME_SIZE(mtu) \
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(sizeof(struct esmem_frame) + FJES_MTU_TO_BUFFER_SIZE(mtu))
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#define FJES_MTU_DEFINE(size) \
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((size) - sizeof(struct esmem_frame) - \
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(ETH_HLEN + VLAN_HLEN + ETH_FCS_LEN))
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#define FJES_DEV_COMMAND_INFO_RES_LEN(epnum) (8 + 2 * (epnum))
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#define FJES_DEV_COMMAND_SHARE_BUFFER_REQ_LEN(txb, rxb) \
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(24 + (8 * ((txb) / EP_BUFFER_INFO_SIZE + (rxb) / EP_BUFFER_INFO_SIZE)))
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#define FJES_DEV_REQ_BUF_SIZE(maxep) \
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FJES_DEV_COMMAND_SHARE_BUFFER_REQ_LEN(EP_BUFFER_SIZE, EP_BUFFER_SIZE)
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#define FJES_DEV_RES_BUF_SIZE(maxep) \
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FJES_DEV_COMMAND_INFO_RES_LEN(maxep)
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/* Frame & MTU */
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struct esmem_frame {
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__le32 frame_size;
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u8 frame_data[];
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};
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/* shared status region */
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struct fjes_device_shared_info {
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int epnum;
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u8 ep_status[];
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};
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/* structures for command control request data*/
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union fjes_device_command_req {
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struct {
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__le32 length;
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} info;
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struct {
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__le32 length;
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__le32 epid;
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__le64 buffer[];
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} share_buffer;
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struct {
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__le32 length;
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__le32 epid;
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} unshare_buffer;
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struct {
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__le32 length;
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__le32 mode;
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__le64 buffer_len;
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__le64 buffer[];
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} start_trace;
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struct {
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__le32 length;
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} stop_trace;
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};
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/* structures for command control response data */
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union fjes_device_command_res {
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struct {
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__le32 length;
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__le32 code;
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struct {
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u8 es_status;
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u8 zone;
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} info[];
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} info;
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struct {
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__le32 length;
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__le32 code;
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} share_buffer;
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struct {
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__le32 length;
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__le32 code;
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} unshare_buffer;
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struct {
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__le32 length;
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__le32 code;
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} start_trace;
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struct {
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__le32 length;
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__le32 code;
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} stop_trace;
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};
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/* parameter for command control */
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struct fjes_device_command_param {
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u32 req_len;
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phys_addr_t req_start;
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u32 res_len;
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phys_addr_t res_start;
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phys_addr_t share_start;
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};
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/* EP buffer information */
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union ep_buffer_info {
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u8 raw[EP_BUFFER_INFO_SIZE];
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struct _ep_buffer_info_common_t {
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u32 version;
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} common;
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struct _ep_buffer_info_v1_t {
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u32 version;
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u32 info_size;
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u32 buffer_size;
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u16 count_max;
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u16 _rsv_1;
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u32 frame_max;
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u8 mac_addr[ETH_ALEN];
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u16 _rsv_2;
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u32 _rsv_3;
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u16 tx_status;
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u16 rx_status;
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u32 head;
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u32 tail;
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u16 vlan_id[EP_BUFFER_SUPPORT_VLAN_MAX];
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} v1i;
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};
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/* buffer pair for Extended Partition */
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struct ep_share_mem_info {
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struct epbuf_handler {
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void *buffer;
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size_t size;
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union ep_buffer_info *info;
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u8 *ring;
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} tx, rx;
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struct rtnl_link_stats64 net_stats;
|
||||
|
||||
u16 tx_status_work;
|
||||
|
||||
u8 es_status;
|
||||
u8 zone;
|
||||
};
|
||||
|
||||
struct es_device_trace {
|
||||
u32 record_num;
|
||||
u32 current_record;
|
||||
u32 status_flag;
|
||||
u32 _rsv;
|
||||
|
||||
struct {
|
||||
u16 epid;
|
||||
u16 dir_offset;
|
||||
u32 data;
|
||||
u64 tsc;
|
||||
} record[];
|
||||
};
|
||||
|
||||
struct fjes_hw_info {
|
||||
struct fjes_device_shared_info *share;
|
||||
union fjes_device_command_req *req_buf;
|
||||
u64 req_buf_size;
|
||||
union fjes_device_command_res *res_buf;
|
||||
u64 res_buf_size;
|
||||
|
||||
int *my_epid;
|
||||
int *max_epid;
|
||||
|
||||
struct es_device_trace *trace;
|
||||
u64 trace_size;
|
||||
|
||||
struct mutex lock; /* buffer lock*/
|
||||
|
||||
unsigned long buffer_share_bit;
|
||||
unsigned long buffer_unshare_reserve_bit;
|
||||
};
|
||||
|
||||
struct fjes_hw {
|
||||
void *back;
|
||||
|
||||
unsigned long txrx_stop_req_bit;
|
||||
unsigned long epstop_req_bit;
|
||||
|
||||
int my_epid;
|
||||
int max_epid;
|
||||
|
||||
struct ep_share_mem_info *ep_shm_info;
|
||||
|
||||
struct fjes_hw_resource {
|
||||
u64 start;
|
||||
u64 size;
|
||||
int irq;
|
||||
} hw_res;
|
||||
|
||||
u8 *base;
|
||||
|
||||
struct fjes_hw_info hw_info;
|
||||
};
|
||||
|
||||
int fjes_hw_init(struct fjes_hw *);
|
||||
int fjes_hw_reset(struct fjes_hw *);
|
||||
|
||||
void fjes_hw_init_command_registers(struct fjes_hw *,
|
||||
struct fjes_device_command_param *);
|
||||
void fjes_hw_setup_epbuf(struct epbuf_handler *, u8 *, u32);
|
||||
void fjes_hw_set_irqmask(struct fjes_hw *, enum REG_ICTL_MASK, bool);
|
||||
|
||||
#endif /* FJES_HW_H_ */
|
||||
|
|
@ -0,0 +1,102 @@
|
|||
/*
|
||||
* FUJITSU Extended Socket Network Device driver
|
||||
* Copyright (c) 2015 FUJITSU LIMITED
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify it
|
||||
* under the terms and conditions of the GNU General Public License,
|
||||
* version 2, as published by the Free Software Foundation.
|
||||
*
|
||||
* This program is distributed in the hope it will be useful, but WITHOUT
|
||||
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
|
||||
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
|
||||
* more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License along with
|
||||
* this program; if not, see <http://www.gnu.org/licenses/>.
|
||||
*
|
||||
* The full GNU General Public License is included in this distribution in
|
||||
* the file called "COPYING".
|
||||
*
|
||||
*/
|
||||
|
||||
#ifndef FJES_REGS_H_
|
||||
#define FJES_REGS_H_
|
||||
|
||||
#include <linux/bitops.h>
|
||||
|
||||
#define XSCT_DEVICE_REGISTER_SIZE 0x1000
|
||||
|
||||
/* register offset */
|
||||
/* Information registers */
|
||||
#define XSCT_OWNER_EPID 0x0000 /* Owner EPID */
|
||||
#define XSCT_MAX_EP 0x0004 /* Maximum EP */
|
||||
|
||||
/* Device Control registers */
|
||||
#define XSCT_DCTL 0x0010 /* Device Control */
|
||||
|
||||
/* Command Control registers */
|
||||
#define XSCT_SHSTSAL 0x0028 /* Share status address Low */
|
||||
#define XSCT_SHSTSAH 0x002C /* Share status address High */
|
||||
|
||||
#define XSCT_REQBL 0x0034 /* Request Buffer length */
|
||||
#define XSCT_REQBAL 0x0038 /* Request Buffer Address Low */
|
||||
#define XSCT_REQBAH 0x003C /* Request Buffer Address High */
|
||||
|
||||
#define XSCT_RESPBL 0x0044 /* Response Buffer Length */
|
||||
#define XSCT_RESPBAL 0x0048 /* Response Buffer Address Low */
|
||||
#define XSCT_RESPBAH 0x004C /* Response Buffer Address High */
|
||||
|
||||
/* Interrupt Control registers */
|
||||
#define XSCT_IMS 0x0084 /* Interrupt mask set */
|
||||
#define XSCT_IMC 0x0088 /* Interrupt mask clear */
|
||||
|
||||
/* register structure */
|
||||
/* Information registers */
|
||||
union REG_OWNER_EPID {
|
||||
struct {
|
||||
__le32 epid:16;
|
||||
__le32:16;
|
||||
} bits;
|
||||
__le32 reg;
|
||||
};
|
||||
|
||||
union REG_MAX_EP {
|
||||
struct {
|
||||
__le32 maxep:16;
|
||||
__le32:16;
|
||||
} bits;
|
||||
__le32 reg;
|
||||
};
|
||||
|
||||
/* Device Control registers */
|
||||
union REG_DCTL {
|
||||
struct {
|
||||
__le32 reset:1;
|
||||
__le32 rsv0:15;
|
||||
__le32 rsv1:16;
|
||||
} bits;
|
||||
__le32 reg;
|
||||
};
|
||||
|
||||
enum REG_ICTL_MASK {
|
||||
REG_ICTL_MASK_INFO_UPDATE = 1 << 20,
|
||||
REG_ICTL_MASK_DEV_STOP_REQ = 1 << 19,
|
||||
REG_ICTL_MASK_TXRX_STOP_REQ = 1 << 18,
|
||||
REG_ICTL_MASK_TXRX_STOP_DONE = 1 << 17,
|
||||
REG_ICTL_MASK_RX_DATA = 1 << 16,
|
||||
REG_ICTL_MASK_ALL = GENMASK(20, 16),
|
||||
};
|
||||
|
||||
struct fjes_hw;
|
||||
|
||||
u32 fjes_hw_rd32(struct fjes_hw *hw, u32 reg);
|
||||
|
||||
#define wr32(reg, val) \
|
||||
do { \
|
||||
u8 *base = hw->base; \
|
||||
writel((val), &base[(reg)]); \
|
||||
} while (0)
|
||||
|
||||
#define rd32(reg) (fjes_hw_rd32(hw, reg))
|
||||
|
||||
#endif /* FJES_REGS_H_ */
|
||||
Loading…
Reference in New Issue