drm/radeon/kms: Add initial support for async DMA on SI
Pretty much the same as cayman. Some changes to the copy packets. Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
This commit is contained in:
Alex Deucher
parent
f60cbd117a
commit
8c5fd7efcc
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@ -797,6 +797,10 @@ void r600_dma_stop(struct radeon_device *rdev);
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int r600_dma_resume(struct radeon_device *rdev);
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void r600_dma_fini(struct radeon_device *rdev);
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void cayman_dma_stop(struct radeon_device *rdev);
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int cayman_dma_resume(struct radeon_device *rdev);
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void cayman_dma_fini(struct radeon_device *rdev);
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/*
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* CS.
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*/
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@ -1731,6 +1731,26 @@ static struct radeon_asic si_asic = {
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.ib_test = &r600_ib_test,
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.is_lockup = &si_gpu_is_lockup,
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.vm_flush = &si_vm_flush,
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},
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[R600_RING_TYPE_DMA_INDEX] = {
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.ib_execute = &cayman_dma_ring_ib_execute,
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.emit_fence = &evergreen_dma_fence_ring_emit,
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.emit_semaphore = &r600_dma_semaphore_ring_emit,
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.cs_parse = NULL,
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.ring_test = &r600_dma_ring_test,
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.ib_test = &r600_dma_ib_test,
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.is_lockup = &cayman_dma_is_lockup,
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.vm_flush = &si_dma_vm_flush,
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},
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[CAYMAN_RING_TYPE_DMA1_INDEX] = {
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.ib_execute = &cayman_dma_ring_ib_execute,
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.emit_fence = &evergreen_dma_fence_ring_emit,
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.emit_semaphore = &r600_dma_semaphore_ring_emit,
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.cs_parse = NULL,
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.ring_test = &r600_dma_ring_test,
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.ib_test = &r600_dma_ib_test,
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.is_lockup = &cayman_dma_is_lockup,
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.vm_flush = &si_dma_vm_flush,
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}
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},
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.irq = {
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@ -1747,8 +1767,8 @@ static struct radeon_asic si_asic = {
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.copy = {
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.blit = NULL,
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.blit_ring_index = RADEON_RING_TYPE_GFX_INDEX,
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.dma = NULL,
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.dma_ring_index = RADEON_RING_TYPE_GFX_INDEX,
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.dma = &si_copy_dma,
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.dma_ring_index = R600_RING_TYPE_DMA_INDEX,
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.copy = NULL,
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.copy_ring_index = RADEON_RING_TYPE_GFX_INDEX,
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},
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@ -501,5 +501,10 @@ void si_vm_set_page(struct radeon_device *rdev, uint64_t pe,
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void si_vm_flush(struct radeon_device *rdev, int ridx, struct radeon_vm *vm);
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int si_ib_parse(struct radeon_device *rdev, struct radeon_ib *ib);
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uint64_t si_get_gpu_clock(struct radeon_device *rdev);
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int si_copy_dma(struct radeon_device *rdev,
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uint64_t src_offset, uint64_t dst_offset,
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unsigned num_gpu_pages,
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struct radeon_fence **fence);
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void si_dma_vm_flush(struct radeon_device *rdev, int ridx, struct radeon_vm *vm);
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#endif
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@ -1660,6 +1660,8 @@ static void si_gpu_init(struct radeon_device *rdev)
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WREG32(GB_ADDR_CONFIG, gb_addr_config);
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WREG32(DMIF_ADDR_CONFIG, gb_addr_config);
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WREG32(HDP_ADDR_CONFIG, gb_addr_config);
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WREG32(DMA_TILING_CONFIG + DMA0_REGISTER_OFFSET, gb_addr_config);
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WREG32(DMA_TILING_CONFIG + DMA1_REGISTER_OFFSET, gb_addr_config);
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si_tiling_mode_table_init(rdev);
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@ -1836,6 +1838,9 @@ static void si_cp_enable(struct radeon_device *rdev, bool enable)
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radeon_ttm_set_active_vram_size(rdev, rdev->mc.visible_vram_size);
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WREG32(CP_ME_CNTL, (CP_ME_HALT | CP_PFP_HALT | CP_CE_HALT));
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WREG32(SCRATCH_UMSK, 0);
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rdev->ring[RADEON_RING_TYPE_GFX_INDEX].ready = false;
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rdev->ring[CAYMAN_RING_TYPE_CP1_INDEX].ready = false;
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rdev->ring[CAYMAN_RING_TYPE_CP2_INDEX].ready = false;
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}
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udelay(50);
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}
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@ -2891,6 +2896,32 @@ void si_vm_flush(struct radeon_device *rdev, int ridx, struct radeon_vm *vm)
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radeon_ring_write(ring, 0x0);
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}
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void si_dma_vm_flush(struct radeon_device *rdev, int ridx, struct radeon_vm *vm)
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{
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struct radeon_ring *ring = &rdev->ring[ridx];
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if (vm == NULL)
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return;
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radeon_ring_write(ring, DMA_PACKET(DMA_PACKET_SRBM_WRITE, 0, 0, 0, 0));
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if (vm->id < 8) {
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radeon_ring_write(ring, (0xf << 16) | ((VM_CONTEXT0_PAGE_TABLE_BASE_ADDR + (vm->id << 2)) >> 2));
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} else {
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radeon_ring_write(ring, (0xf << 16) | ((VM_CONTEXT8_PAGE_TABLE_BASE_ADDR + ((vm->id - 8) << 2)) >> 2));
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}
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radeon_ring_write(ring, vm->pd_gpu_addr >> 12);
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/* flush hdp cache */
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radeon_ring_write(ring, DMA_PACKET(DMA_PACKET_SRBM_WRITE, 0, 0, 0, 0));
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radeon_ring_write(ring, (0xf << 16) | (HDP_MEM_COHERENCY_FLUSH_CNTL >> 2));
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radeon_ring_write(ring, 1);
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/* bits 0-7 are the VM contexts0-7 */
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radeon_ring_write(ring, DMA_PACKET(DMA_PACKET_SRBM_WRITE, 0, 0, 0, 0));
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radeon_ring_write(ring, (0xf << 16) | (VM_INVALIDATE_REQUEST >> 2));
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radeon_ring_write(ring, 1 << vm->id);
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}
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/*
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* RLC
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*/
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@ -3059,6 +3090,10 @@ static void si_disable_interrupt_state(struct radeon_device *rdev)
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WREG32(CP_INT_CNTL_RING0, CNTX_BUSY_INT_ENABLE | CNTX_EMPTY_INT_ENABLE);
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WREG32(CP_INT_CNTL_RING1, 0);
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WREG32(CP_INT_CNTL_RING2, 0);
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tmp = RREG32(DMA_CNTL + DMA0_REGISTER_OFFSET) & ~TRAP_ENABLE;
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WREG32(DMA_CNTL + DMA0_REGISTER_OFFSET, tmp);
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tmp = RREG32(DMA_CNTL + DMA1_REGISTER_OFFSET) & ~TRAP_ENABLE;
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WREG32(DMA_CNTL + DMA1_REGISTER_OFFSET, tmp);
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WREG32(GRBM_INT_CNTL, 0);
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WREG32(INT_MASK + EVERGREEN_CRTC0_REGISTER_OFFSET, 0);
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WREG32(INT_MASK + EVERGREEN_CRTC1_REGISTER_OFFSET, 0);
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@ -3178,6 +3213,7 @@ int si_irq_set(struct radeon_device *rdev)
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u32 hpd1, hpd2, hpd3, hpd4, hpd5, hpd6;
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u32 grbm_int_cntl = 0;
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u32 grph1 = 0, grph2 = 0, grph3 = 0, grph4 = 0, grph5 = 0, grph6 = 0;
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u32 dma_cntl, dma_cntl1;
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if (!rdev->irq.installed) {
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WARN(1, "Can't enable IRQ/MSI because no handler is installed\n");
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@ -3198,6 +3234,9 @@ int si_irq_set(struct radeon_device *rdev)
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hpd5 = RREG32(DC_HPD5_INT_CONTROL) & ~DC_HPDx_INT_EN;
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hpd6 = RREG32(DC_HPD6_INT_CONTROL) & ~DC_HPDx_INT_EN;
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dma_cntl = RREG32(DMA_CNTL + DMA0_REGISTER_OFFSET) & ~TRAP_ENABLE;
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dma_cntl1 = RREG32(DMA_CNTL + DMA1_REGISTER_OFFSET) & ~TRAP_ENABLE;
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/* enable CP interrupts on all rings */
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if (atomic_read(&rdev->irq.ring_int[RADEON_RING_TYPE_GFX_INDEX])) {
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DRM_DEBUG("si_irq_set: sw int gfx\n");
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@ -3211,6 +3250,15 @@ int si_irq_set(struct radeon_device *rdev)
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DRM_DEBUG("si_irq_set: sw int cp2\n");
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cp_int_cntl2 |= TIME_STAMP_INT_ENABLE;
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}
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if (atomic_read(&rdev->irq.ring_int[R600_RING_TYPE_DMA_INDEX])) {
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DRM_DEBUG("si_irq_set: sw int dma\n");
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dma_cntl |= TRAP_ENABLE;
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}
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if (atomic_read(&rdev->irq.ring_int[CAYMAN_RING_TYPE_DMA1_INDEX])) {
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DRM_DEBUG("si_irq_set: sw int dma1\n");
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dma_cntl1 |= TRAP_ENABLE;
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}
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if (rdev->irq.crtc_vblank_int[0] ||
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atomic_read(&rdev->irq.pflip[0])) {
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DRM_DEBUG("si_irq_set: vblank 0\n");
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@ -3270,6 +3318,9 @@ int si_irq_set(struct radeon_device *rdev)
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WREG32(CP_INT_CNTL_RING1, cp_int_cntl1);
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WREG32(CP_INT_CNTL_RING2, cp_int_cntl2);
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WREG32(DMA_CNTL + DMA0_REGISTER_OFFSET, dma_cntl);
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WREG32(DMA_CNTL + DMA1_REGISTER_OFFSET, dma_cntl1);
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WREG32(GRBM_INT_CNTL, grbm_int_cntl);
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WREG32(INT_MASK + EVERGREEN_CRTC0_REGISTER_OFFSET, crtc1);
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@ -3728,9 +3779,17 @@ restart_ih:
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break;
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}
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break;
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case 224: /* DMA trap event */
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DRM_DEBUG("IH: DMA trap\n");
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radeon_fence_process(rdev, R600_RING_TYPE_DMA_INDEX);
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break;
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case 233: /* GUI IDLE */
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DRM_DEBUG("IH: GUI idle\n");
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break;
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case 244: /* DMA trap event */
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DRM_DEBUG("IH: DMA1 trap\n");
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radeon_fence_process(rdev, CAYMAN_RING_TYPE_DMA1_INDEX);
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break;
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default:
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DRM_DEBUG("Unhandled interrupt: %d %d\n", src_id, src_data);
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break;
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@ -3754,6 +3813,80 @@ restart_ih:
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return IRQ_HANDLED;
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}
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/**
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* si_copy_dma - copy pages using the DMA engine
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*
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* @rdev: radeon_device pointer
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* @src_offset: src GPU address
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* @dst_offset: dst GPU address
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* @num_gpu_pages: number of GPU pages to xfer
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* @fence: radeon fence object
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*
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* Copy GPU paging using the DMA engine (SI).
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* Used by the radeon ttm implementation to move pages if
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* registered as the asic copy callback.
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*/
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int si_copy_dma(struct radeon_device *rdev,
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uint64_t src_offset, uint64_t dst_offset,
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unsigned num_gpu_pages,
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struct radeon_fence **fence)
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{
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struct radeon_semaphore *sem = NULL;
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int ring_index = rdev->asic->copy.dma_ring_index;
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struct radeon_ring *ring = &rdev->ring[ring_index];
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u32 size_in_bytes, cur_size_in_bytes;
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int i, num_loops;
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int r = 0;
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r = radeon_semaphore_create(rdev, &sem);
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if (r) {
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DRM_ERROR("radeon: moving bo (%d).\n", r);
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return r;
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}
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size_in_bytes = (num_gpu_pages << RADEON_GPU_PAGE_SHIFT);
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num_loops = DIV_ROUND_UP(size_in_bytes, 0xfffff);
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r = radeon_ring_lock(rdev, ring, num_loops * 5 + 11);
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if (r) {
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DRM_ERROR("radeon: moving bo (%d).\n", r);
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radeon_semaphore_free(rdev, &sem, NULL);
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return r;
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}
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if (radeon_fence_need_sync(*fence, ring->idx)) {
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radeon_semaphore_sync_rings(rdev, sem, (*fence)->ring,
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ring->idx);
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radeon_fence_note_sync(*fence, ring->idx);
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} else {
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radeon_semaphore_free(rdev, &sem, NULL);
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}
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for (i = 0; i < num_loops; i++) {
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cur_size_in_bytes = size_in_bytes;
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if (cur_size_in_bytes > 0xFFFFF)
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cur_size_in_bytes = 0xFFFFF;
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size_in_bytes -= cur_size_in_bytes;
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radeon_ring_write(ring, DMA_PACKET(DMA_PACKET_COPY, 1, 0, 0, cur_size_in_bytes));
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radeon_ring_write(ring, dst_offset & 0xffffffff);
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radeon_ring_write(ring, src_offset & 0xffffffff);
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radeon_ring_write(ring, upper_32_bits(dst_offset) & 0xff);
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radeon_ring_write(ring, upper_32_bits(src_offset) & 0xff);
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src_offset += cur_size_in_bytes;
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dst_offset += cur_size_in_bytes;
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}
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r = radeon_fence_emit(rdev, fence, ring->idx);
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if (r) {
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radeon_ring_unlock_undo(rdev, ring);
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return r;
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}
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radeon_ring_unlock_commit(rdev, ring);
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radeon_semaphore_free(rdev, &sem, *fence);
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return r;
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}
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/*
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* startup/shutdown callbacks
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*/
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@ -3825,6 +3958,18 @@ static int si_startup(struct radeon_device *rdev)
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return r;
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}
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r = radeon_fence_driver_start_ring(rdev, R600_RING_TYPE_DMA_INDEX);
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if (r) {
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dev_err(rdev->dev, "failed initializing DMA fences (%d).\n", r);
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return r;
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}
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r = radeon_fence_driver_start_ring(rdev, CAYMAN_RING_TYPE_DMA1_INDEX);
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if (r) {
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dev_err(rdev->dev, "failed initializing DMA fences (%d).\n", r);
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return r;
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}
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/* Enable IRQ */
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r = si_irq_init(rdev);
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if (r) {
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@ -3855,6 +4000,22 @@ static int si_startup(struct radeon_device *rdev)
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if (r)
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return r;
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ring = &rdev->ring[R600_RING_TYPE_DMA_INDEX];
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r = radeon_ring_init(rdev, ring, ring->ring_size, R600_WB_DMA_RPTR_OFFSET,
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DMA_RB_RPTR + DMA0_REGISTER_OFFSET,
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DMA_RB_WPTR + DMA0_REGISTER_OFFSET,
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2, 0x3fffc, DMA_PACKET(DMA_PACKET_NOP, 0, 0, 0, 0));
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if (r)
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return r;
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ring = &rdev->ring[CAYMAN_RING_TYPE_DMA1_INDEX];
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r = radeon_ring_init(rdev, ring, ring->ring_size, CAYMAN_WB_DMA1_RPTR_OFFSET,
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DMA_RB_RPTR + DMA1_REGISTER_OFFSET,
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DMA_RB_WPTR + DMA1_REGISTER_OFFSET,
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2, 0x3fffc, DMA_PACKET(DMA_PACKET_NOP, 0, 0, 0, 0));
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if (r)
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return r;
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r = si_cp_load_microcode(rdev);
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if (r)
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return r;
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@ -3862,6 +4023,10 @@ static int si_startup(struct radeon_device *rdev)
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if (r)
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return r;
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r = cayman_dma_resume(rdev);
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if (r)
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return r;
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r = radeon_ib_pool_init(rdev);
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if (r) {
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dev_err(rdev->dev, "IB initialization failed (%d).\n", r);
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@ -3903,9 +4068,7 @@ int si_resume(struct radeon_device *rdev)
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int si_suspend(struct radeon_device *rdev)
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{
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si_cp_enable(rdev, false);
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rdev->ring[RADEON_RING_TYPE_GFX_INDEX].ready = false;
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rdev->ring[CAYMAN_RING_TYPE_CP1_INDEX].ready = false;
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rdev->ring[CAYMAN_RING_TYPE_CP2_INDEX].ready = false;
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cayman_dma_stop(rdev);
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si_irq_suspend(rdev);
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radeon_wb_disable(rdev);
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si_pcie_gart_disable(rdev);
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@ -3983,6 +4146,14 @@ int si_init(struct radeon_device *rdev)
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ring->ring_obj = NULL;
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r600_ring_init(rdev, ring, 1024 * 1024);
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ring = &rdev->ring[R600_RING_TYPE_DMA_INDEX];
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ring->ring_obj = NULL;
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r600_ring_init(rdev, ring, 64 * 1024);
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ring = &rdev->ring[CAYMAN_RING_TYPE_DMA1_INDEX];
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ring->ring_obj = NULL;
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r600_ring_init(rdev, ring, 64 * 1024);
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rdev->ih.ring_obj = NULL;
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r600_ih_ring_init(rdev, 64 * 1024);
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@ -3995,6 +4166,7 @@ int si_init(struct radeon_device *rdev)
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if (r) {
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dev_err(rdev->dev, "disabling GPU acceleration\n");
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si_cp_fini(rdev);
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cayman_dma_fini(rdev);
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si_irq_fini(rdev);
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si_rlc_fini(rdev);
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radeon_wb_fini(rdev);
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@ -4023,6 +4195,7 @@ void si_fini(struct radeon_device *rdev)
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r600_blit_fini(rdev);
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#endif
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si_cp_fini(rdev);
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cayman_dma_fini(rdev);
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si_irq_fini(rdev);
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si_rlc_fini(rdev);
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radeon_wb_fini(rdev);
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@ -936,4 +936,51 @@
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#define PACKET3_WAIT_ON_AVAIL_BUFFER 0x8A
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#define PACKET3_SWITCH_BUFFER 0x8B
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/* ASYNC DMA - first instance at 0xd000, second at 0xd800 */
|
||||
#define DMA0_REGISTER_OFFSET 0x0 /* not a register */
|
||||
#define DMA1_REGISTER_OFFSET 0x800 /* not a register */
|
||||
|
||||
#define DMA_RB_CNTL 0xd000
|
||||
# define DMA_RB_ENABLE (1 << 0)
|
||||
# define DMA_RB_SIZE(x) ((x) << 1) /* log2 */
|
||||
# define DMA_RB_SWAP_ENABLE (1 << 9) /* 8IN32 */
|
||||
# define DMA_RPTR_WRITEBACK_ENABLE (1 << 12)
|
||||
# define DMA_RPTR_WRITEBACK_SWAP_ENABLE (1 << 13) /* 8IN32 */
|
||||
# define DMA_RPTR_WRITEBACK_TIMER(x) ((x) << 16) /* log2 */
|
||||
#define DMA_RB_BASE 0xd004
|
||||
#define DMA_RB_RPTR 0xd008
|
||||
#define DMA_RB_WPTR 0xd00c
|
||||
|
||||
#define DMA_RB_RPTR_ADDR_HI 0xd01c
|
||||
#define DMA_RB_RPTR_ADDR_LO 0xd020
|
||||
|
||||
#define DMA_IB_CNTL 0xd024
|
||||
# define DMA_IB_ENABLE (1 << 0)
|
||||
# define DMA_IB_SWAP_ENABLE (1 << 4)
|
||||
#define DMA_IB_RPTR 0xd028
|
||||
#define DMA_CNTL 0xd02c
|
||||
# define TRAP_ENABLE (1 << 0)
|
||||
# define SEM_INCOMPLETE_INT_ENABLE (1 << 1)
|
||||
# define SEM_WAIT_INT_ENABLE (1 << 2)
|
||||
# define DATA_SWAP_ENABLE (1 << 3)
|
||||
# define FENCE_SWAP_ENABLE (1 << 4)
|
||||
# define CTXEMPTY_INT_ENABLE (1 << 28)
|
||||
#define DMA_TILING_CONFIG 0xd0b8
|
||||
|
||||
#define DMA_PACKET(cmd, b, t, s, n) ((((cmd) & 0xF) << 28) | \
|
||||
(((b) & 0x1) << 26) | \
|
||||
(((t) & 0x1) << 23) | \
|
||||
(((s) & 0x1) << 22) | \
|
||||
(((n) & 0xFFFFF) << 0))
|
||||
/* async DMA Packet types */
|
||||
#define DMA_PACKET_WRITE 0x2
|
||||
#define DMA_PACKET_COPY 0x3
|
||||
#define DMA_PACKET_INDIRECT_BUFFER 0x4
|
||||
#define DMA_PACKET_SEMAPHORE 0x5
|
||||
#define DMA_PACKET_FENCE 0x6
|
||||
#define DMA_PACKET_TRAP 0x7
|
||||
#define DMA_PACKET_SRBM_WRITE 0x9
|
||||
#define DMA_PACKET_CONSTANT_FILL 0xd
|
||||
#define DMA_PACKET_NOP 0xf
|
||||
|
||||
#endif
|
||||
|
|
|
|||
Loading…
Reference in New Issue