Revert "drm/amdgpu: remove fence fallback"
This reverts commit 9b0df0937a852d299fbe42a5939c9a8a4cc83c55. This commit breaks KCQ IB test and S3 on Polaris 11. Signed-off-by: Andrey Grodzovsky <andrey.grodzovsky@amd.com> Acked-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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@ -146,6 +146,7 @@ extern int amdgpu_cik_support;
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#define AMDGPU_DEFAULT_GTT_SIZE_MB 3072ULL /* 3GB by default */
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#define AMDGPU_WAIT_IDLE_TIMEOUT_IN_MS 3000
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#define AMDGPU_MAX_USEC_TIMEOUT 100000 /* 100 ms */
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#define AMDGPU_FENCE_JIFFIES_TIMEOUT (HZ / 2)
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/* AMDGPU_IB_POOL_SIZE must be a power of 2 */
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#define AMDGPU_IB_POOL_SIZE 16
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#define AMDGPU_DEBUGFS_MAX_COMPONENTS 32
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@ -195,6 +195,19 @@ int amdgpu_fence_emit_polling(struct amdgpu_ring *ring, uint32_t *s)
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return 0;
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}
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/**
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* amdgpu_fence_schedule_fallback - schedule fallback check
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*
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* @ring: pointer to struct amdgpu_ring
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*
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* Start a timer as fallback to our interrupts.
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*/
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static void amdgpu_fence_schedule_fallback(struct amdgpu_ring *ring)
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{
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mod_timer(&ring->fence_drv.fallback_timer,
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jiffies + AMDGPU_FENCE_JIFFIES_TIMEOUT);
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}
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/**
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* amdgpu_fence_process - check for fence activity
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*
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@ -216,6 +229,9 @@ void amdgpu_fence_process(struct amdgpu_ring *ring)
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} while (atomic_cmpxchg(&drv->last_seq, last_seq, seq) != last_seq);
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if (seq != ring->fence_drv.sync_seq)
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amdgpu_fence_schedule_fallback(ring);
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if (unlikely(seq == last_seq))
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return;
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@ -246,6 +262,21 @@ void amdgpu_fence_process(struct amdgpu_ring *ring)
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} while (last_seq != seq);
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}
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/**
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* amdgpu_fence_fallback - fallback for hardware interrupts
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*
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* @work: delayed work item
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*
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* Checks for fence activity.
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*/
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static void amdgpu_fence_fallback(struct timer_list *t)
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{
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struct amdgpu_ring *ring = from_timer(ring, t,
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fence_drv.fallback_timer);
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amdgpu_fence_process(ring);
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}
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/**
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* amdgpu_fence_wait_empty - wait for all fences to signal
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*
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@ -393,6 +424,8 @@ int amdgpu_fence_driver_init_ring(struct amdgpu_ring *ring,
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atomic_set(&ring->fence_drv.last_seq, 0);
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ring->fence_drv.initialized = false;
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timer_setup(&ring->fence_drv.fallback_timer, amdgpu_fence_fallback, 0);
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ring->fence_drv.num_fences_mask = num_hw_submission * 2 - 1;
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spin_lock_init(&ring->fence_drv.lock);
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ring->fence_drv.fences = kcalloc(num_hw_submission * 2, sizeof(void *),
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@ -468,6 +501,7 @@ void amdgpu_fence_driver_fini(struct amdgpu_device *adev)
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amdgpu_irq_put(adev, ring->fence_drv.irq_src,
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ring->fence_drv.irq_type);
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drm_sched_fini(&ring->sched);
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del_timer_sync(&ring->fence_drv.fallback_timer);
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for (j = 0; j <= ring->fence_drv.num_fences_mask; ++j)
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dma_fence_put(ring->fence_drv.fences[j]);
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kfree(ring->fence_drv.fences);
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@ -560,6 +594,27 @@ static const char *amdgpu_fence_get_timeline_name(struct dma_fence *f)
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return (const char *)fence->ring->name;
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}
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/**
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* amdgpu_fence_enable_signaling - enable signalling on fence
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* @fence: fence
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*
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* This function is called with fence_queue lock held, and adds a callback
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* to fence_queue that checks if this fence is signaled, and if so it
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* signals the fence and removes itself.
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*/
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static bool amdgpu_fence_enable_signaling(struct dma_fence *f)
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{
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struct amdgpu_fence *fence = to_amdgpu_fence(f);
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struct amdgpu_ring *ring = fence->ring;
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if (!timer_pending(&ring->fence_drv.fallback_timer))
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amdgpu_fence_schedule_fallback(ring);
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DMA_FENCE_TRACE(&fence->base, "armed on ring %i!\n", ring->idx);
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return true;
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}
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/**
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* amdgpu_fence_free - free up the fence memory
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*
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@ -590,6 +645,7 @@ static void amdgpu_fence_release(struct dma_fence *f)
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static const struct dma_fence_ops amdgpu_fence_ops = {
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.get_driver_name = amdgpu_fence_get_driver_name,
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.get_timeline_name = amdgpu_fence_get_timeline_name,
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.enable_signaling = amdgpu_fence_enable_signaling,
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.release = amdgpu_fence_release,
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};
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@ -77,6 +77,7 @@ struct amdgpu_fence_driver {
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bool initialized;
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struct amdgpu_irq_src *irq_src;
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unsigned irq_type;
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struct timer_list fallback_timer;
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unsigned num_fences_mask;
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spinlock_t lock;
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struct dma_fence **fences;
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