This pull request contains Broadcom ARM/ARM64 SoCs specific driver changes for
4.13, please pull the following: - Doug adds support for the latest generation GISB bus arbiter (v7), he starts by fixing two issues in how registers are written, and how 64-bit addresses are captured and then he simplifies the error interception by using notifiers, which allows him to add support for ARM64 - Markus updates the SOC_BRCMSTB Kconfig depends to cover ARM64 and BMIPS_GENERIC systems where this code is now also used -----BEGIN PGP SIGNATURE----- iQIcBAABCAAGBQJZPs6qAAoJEIfQlpxEBwcE6y8QAOMSWs50jnXn5zJzYxXENsgo 2tByeT/eQDkCyEvXPQ8igqqw/3eSuEJJZe0218MOo3aoAteBV2hzx0z59YNxL6nM oCO+p2WBNZ+LlIkewfGNWgmtd8nFqaH1nhm0Gg2lPhwgNikwDXRrfXcTu8ppJLzb V2CuDZh5ZGkL7QM6UMFeHiFW66mCcvhu/WanbrhLN8FgocHLjZKyVaduSvybQiF3 I8afwCVzDq6Aa2lYxNKSeQm0ionhgyei3PcmiJAGSaVMYG0X7qJjKsaXltRe5lhn a2JUp+X0AhuV/Ulr6xCMD6j4DK8czK1Nsj4f2u5Ld0fg+yrCE0bjY1QY/nU7zjCt aeYbpeRXiU1T1YSdnx0YkDezSe63nO9Vrmsa9SQp23e1Z0MPoRMJeDOHJZ4LtQwt mkavMwj7f5P1NqDh5HrcAsga/4qmC0KUMmQTKBPze82nLuOoYjGWLroMEuALL5yI YfkAxBRQr2Ep7Bf5Ska2FDQqnkrv2T/gnMHTqJ6H1ciHsk3C/Z52Px8QZA5ZMjhf kELlrKjdVDr1Yldf2rmsOv7GMfPXod9r0G6fgsGrhyoiHVNaChdo78DtVg4ITY7v RHSXX/ehZmQpPokQOtguxgSmL5QksUDwTf1S2q3iaWaZdu7eZtkjOQe1AwYrnzse s5hQW4oVSEfgXuR66jPa =Skk5 -----END PGP SIGNATURE----- Merge tag 'arm-soc/for-4.13/drivers' of http://github.com/Broadcom/stblinux into next/drivers This pull request contains Broadcom ARM/ARM64 SoCs specific driver changes for 4.13, please pull the following: - Doug adds support for the latest generation GISB bus arbiter (v7), he starts by fixing two issues in how registers are written, and how 64-bit addresses are captured and then he simplifies the error interception by using notifiers, which allows him to add support for ARM64 - Markus updates the SOC_BRCMSTB Kconfig depends to cover ARM64 and BMIPS_GENERIC systems where this code is now also used * tag 'arm-soc/for-4.13/drivers' of http://github.com/Broadcom/stblinux: soc: brcmstb: enable drivers for ARM64 and BMIPS bus: brcmstb_gisb: update to support new revision bus: brcmstb_gisb: enable driver for ARM64 architecture bus: brcmstb_gisb: remove low-level ARM hooks bus: brcmstb_gisb: add notifier handling bus: brcmstb_gisb: correct support for 64-bit address output bus: brcmstb_gisb: Use register offsets with writes too Signed-off-by: Olof Johansson <olof@lixom.net>
This commit is contained in:
Olof Johansson
commit
8c2f8a2fb1
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@ -3,7 +3,8 @@ Broadcom GISB bus Arbiter controller
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Required properties:
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- compatible:
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"brcm,gisb-arb" or "brcm,bcm7445-gisb-arb" for 28nm chips
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"brcm,bcm7278-gisb-arb" for V7 28nm chips
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"brcm,gisb-arb" or "brcm,bcm7445-gisb-arb" for other 28nm chips
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"brcm,bcm7435-gisb-arb" for newer 40nm chips
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"brcm,bcm7400-gisb-arb" for older 40nm chips and all 65nm chips
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"brcm,bcm7038-gisb-arb" for 130nm chips
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@ -57,7 +57,7 @@ config ARM_CCN
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config BRCMSTB_GISB_ARB
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bool "Broadcom STB GISB bus arbiter"
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depends on ARM || MIPS
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depends on ARM || ARM64 || MIPS
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default ARCH_BRCMSTB || BMIPS_GENERIC
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help
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Driver for the Broadcom Set Top Box System-on-a-chip internal bus
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@ -1,5 +1,5 @@
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/*
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* Copyright (C) 2014 Broadcom Corporation
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* Copyright (C) 2014-2017 Broadcom
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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@ -24,11 +24,9 @@
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#include <linux/of.h>
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#include <linux/bitops.h>
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#include <linux/pm.h>
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#ifdef CONFIG_ARM
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#include <asm/bug.h>
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#include <asm/signal.h>
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#endif
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#include <linux/kernel.h>
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#include <linux/kdebug.h>
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#include <linux/notifier.h>
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#ifdef CONFIG_MIPS
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#include <asm/traps.h>
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@ -37,8 +35,6 @@
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#define ARB_ERR_CAP_CLEAR (1 << 0)
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#define ARB_ERR_CAP_STATUS_TIMEOUT (1 << 12)
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#define ARB_ERR_CAP_STATUS_TEA (1 << 11)
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#define ARB_ERR_CAP_STATUS_BS_SHIFT (1 << 2)
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#define ARB_ERR_CAP_STATUS_BS_MASK 0x3c
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#define ARB_ERR_CAP_STATUS_WRITE (1 << 1)
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#define ARB_ERR_CAP_STATUS_VALID (1 << 0)
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@ -47,7 +43,6 @@ enum {
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ARB_ERR_CAP_CLR,
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ARB_ERR_CAP_HI_ADDR,
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ARB_ERR_CAP_ADDR,
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ARB_ERR_CAP_DATA,
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ARB_ERR_CAP_STATUS,
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ARB_ERR_CAP_MASTER,
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};
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@ -57,17 +52,24 @@ static const int gisb_offsets_bcm7038[] = {
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[ARB_ERR_CAP_CLR] = 0x0c4,
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[ARB_ERR_CAP_HI_ADDR] = -1,
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[ARB_ERR_CAP_ADDR] = 0x0c8,
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[ARB_ERR_CAP_DATA] = 0x0cc,
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[ARB_ERR_CAP_STATUS] = 0x0d0,
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[ARB_ERR_CAP_MASTER] = -1,
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};
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static const int gisb_offsets_bcm7278[] = {
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[ARB_TIMER] = 0x008,
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[ARB_ERR_CAP_CLR] = 0x7f8,
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[ARB_ERR_CAP_HI_ADDR] = -1,
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[ARB_ERR_CAP_ADDR] = 0x7e0,
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[ARB_ERR_CAP_STATUS] = 0x7f0,
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[ARB_ERR_CAP_MASTER] = 0x7f4,
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};
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static const int gisb_offsets_bcm7400[] = {
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[ARB_TIMER] = 0x00c,
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[ARB_ERR_CAP_CLR] = 0x0c8,
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[ARB_ERR_CAP_HI_ADDR] = -1,
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[ARB_ERR_CAP_ADDR] = 0x0cc,
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[ARB_ERR_CAP_DATA] = 0x0d0,
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[ARB_ERR_CAP_STATUS] = 0x0d4,
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[ARB_ERR_CAP_MASTER] = 0x0d8,
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};
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@ -77,7 +79,6 @@ static const int gisb_offsets_bcm7435[] = {
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[ARB_ERR_CAP_CLR] = 0x168,
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[ARB_ERR_CAP_HI_ADDR] = -1,
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[ARB_ERR_CAP_ADDR] = 0x16c,
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[ARB_ERR_CAP_DATA] = 0x170,
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[ARB_ERR_CAP_STATUS] = 0x174,
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[ARB_ERR_CAP_MASTER] = 0x178,
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};
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@ -87,7 +88,6 @@ static const int gisb_offsets_bcm7445[] = {
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[ARB_ERR_CAP_CLR] = 0x7e4,
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[ARB_ERR_CAP_HI_ADDR] = 0x7e8,
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[ARB_ERR_CAP_ADDR] = 0x7ec,
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[ARB_ERR_CAP_DATA] = 0x7f0,
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[ARB_ERR_CAP_STATUS] = 0x7f4,
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[ARB_ERR_CAP_MASTER] = 0x7f8,
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};
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@ -109,9 +109,13 @@ static u32 gisb_read(struct brcmstb_gisb_arb_device *gdev, int reg)
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{
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int offset = gdev->gisb_offsets[reg];
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if (offset < 0) {
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/* return 1 if the hardware doesn't have ARB_ERR_CAP_MASTER */
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if (offset == -1)
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if (reg == ARB_ERR_CAP_MASTER)
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return 1;
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else
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return 0;
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}
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if (gdev->big_endian)
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return ioread32be(gdev->base + offset);
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@ -119,6 +123,16 @@ static u32 gisb_read(struct brcmstb_gisb_arb_device *gdev, int reg)
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return ioread32(gdev->base + offset);
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}
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static u64 gisb_read_address(struct brcmstb_gisb_arb_device *gdev)
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{
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u64 value;
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value = gisb_read(gdev, ARB_ERR_CAP_ADDR);
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value |= (u64)gisb_read(gdev, ARB_ERR_CAP_HI_ADDR) << 32;
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return value;
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}
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static void gisb_write(struct brcmstb_gisb_arb_device *gdev, u32 val, int reg)
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{
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int offset = gdev->gisb_offsets[reg];
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@ -127,9 +141,9 @@ static void gisb_write(struct brcmstb_gisb_arb_device *gdev, u32 val, int reg)
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return;
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if (gdev->big_endian)
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iowrite32be(val, gdev->base + reg);
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iowrite32be(val, gdev->base + offset);
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else
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iowrite32(val, gdev->base + reg);
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iowrite32(val, gdev->base + offset);
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}
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static ssize_t gisb_arb_get_timeout(struct device *dev,
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@ -185,7 +199,7 @@ static int brcmstb_gisb_arb_decode_addr(struct brcmstb_gisb_arb_device *gdev,
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const char *reason)
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{
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u32 cap_status;
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unsigned long arb_addr;
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u64 arb_addr;
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u32 master;
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const char *m_name;
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char m_fmt[11];
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@ -197,10 +211,7 @@ static int brcmstb_gisb_arb_decode_addr(struct brcmstb_gisb_arb_device *gdev,
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return 1;
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/* Read the address and master */
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arb_addr = gisb_read(gdev, ARB_ERR_CAP_ADDR) & 0xffffffff;
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#if (IS_ENABLED(CONFIG_PHYS_ADDR_T_64BIT))
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arb_addr |= (u64)gisb_read(gdev, ARB_ERR_CAP_HI_ADDR) << 32;
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#endif
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arb_addr = gisb_read_address(gdev);
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master = gisb_read(gdev, ARB_ERR_CAP_MASTER);
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m_name = brcmstb_gisb_master_to_str(gdev, master);
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@ -209,7 +220,7 @@ static int brcmstb_gisb_arb_decode_addr(struct brcmstb_gisb_arb_device *gdev,
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m_name = m_fmt;
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}
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pr_crit("%s: %s at 0x%lx [%c %s], core: %s\n",
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pr_crit("%s: %s at 0x%llx [%c %s], core: %s\n",
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__func__, reason, arb_addr,
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cap_status & ARB_ERR_CAP_STATUS_WRITE ? 'W' : 'R',
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cap_status & ARB_ERR_CAP_STATUS_TIMEOUT ? "timeout" : "",
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@ -221,27 +232,6 @@ static int brcmstb_gisb_arb_decode_addr(struct brcmstb_gisb_arb_device *gdev,
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return 0;
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}
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#ifdef CONFIG_ARM
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static int brcmstb_bus_error_handler(unsigned long addr, unsigned int fsr,
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struct pt_regs *regs)
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{
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int ret = 0;
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struct brcmstb_gisb_arb_device *gdev;
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/* iterate over each GISB arb registered handlers */
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list_for_each_entry(gdev, &brcmstb_gisb_arb_device_list, next)
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ret |= brcmstb_gisb_arb_decode_addr(gdev, "bus error");
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/*
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* If it was an imprecise abort, then we need to correct the
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* return address to be _after_ the instruction.
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*/
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if (fsr & (1 << 10))
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regs->ARM_pc += 4;
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return ret;
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}
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#endif
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#ifdef CONFIG_MIPS
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static int brcmstb_bus_error_handler(struct pt_regs *regs, int is_fixup)
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{
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@ -279,6 +269,36 @@ static irqreturn_t brcmstb_gisb_tea_handler(int irq, void *dev_id)
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return IRQ_HANDLED;
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}
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/*
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* Dump out gisb errors on die or panic.
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*/
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static int dump_gisb_error(struct notifier_block *self, unsigned long v,
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void *p);
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static struct notifier_block gisb_die_notifier = {
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.notifier_call = dump_gisb_error,
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};
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static struct notifier_block gisb_panic_notifier = {
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.notifier_call = dump_gisb_error,
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};
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static int dump_gisb_error(struct notifier_block *self, unsigned long v,
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void *p)
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{
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struct brcmstb_gisb_arb_device *gdev;
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const char *reason = "panic";
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if (self == &gisb_die_notifier)
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reason = "die";
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/* iterate over each GISB arb registered handlers */
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list_for_each_entry(gdev, &brcmstb_gisb_arb_device_list, next)
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brcmstb_gisb_arb_decode_addr(gdev, reason);
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return NOTIFY_DONE;
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}
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static DEVICE_ATTR(gisb_arb_timeout, S_IWUSR | S_IRUGO,
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gisb_arb_get_timeout, gisb_arb_set_timeout);
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@ -296,6 +316,7 @@ static const struct of_device_id brcmstb_gisb_arb_of_match[] = {
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{ .compatible = "brcm,bcm7445-gisb-arb", .data = gisb_offsets_bcm7445 },
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{ .compatible = "brcm,bcm7435-gisb-arb", .data = gisb_offsets_bcm7435 },
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{ .compatible = "brcm,bcm7400-gisb-arb", .data = gisb_offsets_bcm7400 },
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{ .compatible = "brcm,bcm7278-gisb-arb", .data = gisb_offsets_bcm7278 },
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{ .compatible = "brcm,bcm7038-gisb-arb", .data = gisb_offsets_bcm7038 },
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{ },
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};
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@ -378,14 +399,16 @@ static int __init brcmstb_gisb_arb_probe(struct platform_device *pdev)
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list_add_tail(&gdev->next, &brcmstb_gisb_arb_device_list);
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#ifdef CONFIG_ARM
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hook_fault_code(22, brcmstb_bus_error_handler, SIGBUS, 0,
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"imprecise external abort");
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#endif
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#ifdef CONFIG_MIPS
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board_be_handler = brcmstb_bus_error_handler;
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#endif
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if (list_is_singular(&brcmstb_gisb_arb_device_list)) {
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register_die_notifier(&gisb_die_notifier);
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atomic_notifier_chain_register(&panic_notifier_list,
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&gisb_panic_notifier);
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}
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dev_info(&pdev->dev, "registered mem: %p, irqs: %d, %d\n",
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gdev->base, timeout_irq, tea_irq);
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@ -11,7 +11,7 @@ config RASPBERRYPI_POWER
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config SOC_BRCMSTB
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bool "Broadcom STB SoC drivers"
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depends on ARM
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depends on ARM || ARM64 || BMIPS_GENERIC || COMPILE_TEST
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select SOC_BUS
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help
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Enables drivers for the Broadcom Set-Top Box (STB) series of chips.
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