drm/amdgpu: only allow secure submission on rings which support that
Only GFX ring, SDMA ring and VCN decode ring support secure submission at the moment. Suggested-by: Christian König <christian.koenig@amd.com> Signed-off-by: Lang Yu <Lang.Yu@amd.com> Reviewed-by: Christian König <christian.koenig@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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@ -166,8 +166,8 @@ int amdgpu_ib_schedule(struct amdgpu_ring *ring, unsigned num_ibs,
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}
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if ((ib->flags & AMDGPU_IB_FLAGS_SECURE) &&
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(ring->funcs->type == AMDGPU_RING_TYPE_COMPUTE)) {
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dev_err(adev->dev, "secure submissions not supported on compute rings\n");
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(!ring->funcs->secure_submission_supported)) {
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dev_err(adev->dev, "secure submissions not supported on ring <%s>\n", ring->name);
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return -EINVAL;
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}
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@ -155,6 +155,7 @@ struct amdgpu_ring_funcs {
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u32 nop;
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bool support_64bit_ptrs;
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bool no_user_fence;
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bool secure_submission_supported;
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unsigned vmhub;
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unsigned extra_dw;
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@ -9377,6 +9377,7 @@ static const struct amdgpu_ring_funcs gfx_v10_0_ring_funcs_gfx = {
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.align_mask = 0xff,
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.nop = PACKET3(PACKET3_NOP, 0x3FFF),
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.support_64bit_ptrs = true,
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.secure_submission_supported = true,
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.vmhub = AMDGPU_GFXHUB_0,
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.get_rptr = gfx_v10_0_ring_get_rptr_gfx,
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.get_wptr = gfx_v10_0_ring_get_wptr_gfx,
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@ -6865,6 +6865,7 @@ static const struct amdgpu_ring_funcs gfx_v9_0_ring_funcs_gfx = {
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.align_mask = 0xff,
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.nop = PACKET3(PACKET3_NOP, 0x3FFF),
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.support_64bit_ptrs = true,
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.secure_submission_supported = true,
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.vmhub = AMDGPU_GFXHUB_0,
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.get_rptr = gfx_v9_0_ring_get_rptr_gfx,
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.get_wptr = gfx_v9_0_ring_get_wptr_gfx,
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@ -1142,6 +1142,7 @@ static const struct amdgpu_ring_funcs sdma_v2_4_ring_funcs = {
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.align_mask = 0xf,
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.nop = SDMA_PKT_NOP_HEADER_OP(SDMA_OP_NOP),
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.support_64bit_ptrs = false,
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.secure_submission_supported = true,
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.get_rptr = sdma_v2_4_ring_get_rptr,
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.get_wptr = sdma_v2_4_ring_get_wptr,
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.set_wptr = sdma_v2_4_ring_set_wptr,
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@ -1580,6 +1580,7 @@ static const struct amdgpu_ring_funcs sdma_v3_0_ring_funcs = {
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.align_mask = 0xf,
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.nop = SDMA_PKT_NOP_HEADER_OP(SDMA_OP_NOP),
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.support_64bit_ptrs = false,
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.secure_submission_supported = true,
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.get_rptr = sdma_v3_0_ring_get_rptr,
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.get_wptr = sdma_v3_0_ring_get_wptr,
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.set_wptr = sdma_v3_0_ring_set_wptr,
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@ -2414,6 +2414,7 @@ static const struct amdgpu_ring_funcs sdma_v4_0_ring_funcs = {
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.align_mask = 0xf,
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.nop = SDMA_PKT_NOP_HEADER_OP(SDMA_OP_NOP),
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.support_64bit_ptrs = true,
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.secure_submission_supported = true,
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.vmhub = AMDGPU_MMHUB_0,
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.get_rptr = sdma_v4_0_ring_get_rptr,
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.get_wptr = sdma_v4_0_ring_get_wptr,
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@ -2450,6 +2451,7 @@ static const struct amdgpu_ring_funcs sdma_v4_0_ring_funcs_2nd_mmhub = {
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.align_mask = 0xf,
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.nop = SDMA_PKT_NOP_HEADER_OP(SDMA_OP_NOP),
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.support_64bit_ptrs = true,
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.secure_submission_supported = true,
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.vmhub = AMDGPU_MMHUB_1,
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.get_rptr = sdma_v4_0_ring_get_rptr,
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.get_wptr = sdma_v4_0_ring_get_wptr,
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@ -2482,6 +2484,7 @@ static const struct amdgpu_ring_funcs sdma_v4_0_page_ring_funcs = {
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.align_mask = 0xf,
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.nop = SDMA_PKT_NOP_HEADER_OP(SDMA_OP_NOP),
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.support_64bit_ptrs = true,
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.secure_submission_supported = true,
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.vmhub = AMDGPU_MMHUB_0,
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.get_rptr = sdma_v4_0_ring_get_rptr,
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.get_wptr = sdma_v4_0_page_ring_get_wptr,
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@ -2514,6 +2517,7 @@ static const struct amdgpu_ring_funcs sdma_v4_0_page_ring_funcs_2nd_mmhub = {
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.align_mask = 0xf,
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.nop = SDMA_PKT_NOP_HEADER_OP(SDMA_OP_NOP),
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.support_64bit_ptrs = true,
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.secure_submission_supported = true,
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.vmhub = AMDGPU_MMHUB_1,
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.get_rptr = sdma_v4_0_ring_get_rptr,
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.get_wptr = sdma_v4_0_page_ring_get_wptr,
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@ -1690,6 +1690,7 @@ static const struct amdgpu_ring_funcs sdma_v5_0_ring_funcs = {
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.align_mask = 0xf,
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.nop = SDMA_PKT_NOP_HEADER_OP(SDMA_OP_NOP),
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.support_64bit_ptrs = true,
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.secure_submission_supported = true,
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.vmhub = AMDGPU_GFXHUB_0,
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.get_rptr = sdma_v5_0_ring_get_rptr,
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.get_wptr = sdma_v5_0_ring_get_wptr,
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@ -1687,6 +1687,7 @@ static const struct amdgpu_ring_funcs sdma_v5_2_ring_funcs = {
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.align_mask = 0xf,
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.nop = SDMA_PKT_NOP_HEADER_OP(SDMA_OP_NOP),
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.support_64bit_ptrs = true,
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.secure_submission_supported = true,
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.vmhub = AMDGPU_GFXHUB_0,
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.get_rptr = sdma_v5_2_ring_get_rptr,
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.get_wptr = sdma_v5_2_ring_get_wptr,
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@ -1910,6 +1910,7 @@ static const struct amdgpu_ring_funcs vcn_v1_0_dec_ring_vm_funcs = {
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.align_mask = 0xf,
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.support_64bit_ptrs = false,
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.no_user_fence = true,
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.secure_submission_supported = true,
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.vmhub = AMDGPU_MMHUB_0,
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.get_rptr = vcn_v1_0_dec_ring_get_rptr,
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.get_wptr = vcn_v1_0_dec_ring_get_wptr,
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@ -2007,6 +2007,7 @@ static const struct amd_ip_funcs vcn_v2_0_ip_funcs = {
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static const struct amdgpu_ring_funcs vcn_v2_0_dec_ring_vm_funcs = {
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.type = AMDGPU_RING_TYPE_VCN_DEC,
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.align_mask = 0xf,
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.secure_submission_supported = true,
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.vmhub = AMDGPU_MMHUB_0,
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.get_rptr = vcn_v2_0_dec_ring_get_rptr,
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.get_wptr = vcn_v2_0_dec_ring_get_wptr,
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@ -1515,6 +1515,7 @@ static void vcn_v2_5_dec_ring_set_wptr(struct amdgpu_ring *ring)
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static const struct amdgpu_ring_funcs vcn_v2_5_dec_ring_vm_funcs = {
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.type = AMDGPU_RING_TYPE_VCN_DEC,
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.align_mask = 0xf,
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.secure_submission_supported = true,
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.vmhub = AMDGPU_MMHUB_1,
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.get_rptr = vcn_v2_5_dec_ring_get_rptr,
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.get_wptr = vcn_v2_5_dec_ring_get_wptr,
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@ -1545,6 +1546,7 @@ static const struct amdgpu_ring_funcs vcn_v2_5_dec_ring_vm_funcs = {
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static const struct amdgpu_ring_funcs vcn_v2_6_dec_ring_vm_funcs = {
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.type = AMDGPU_RING_TYPE_VCN_DEC,
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.align_mask = 0xf,
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.secure_submission_supported = true,
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.vmhub = AMDGPU_MMHUB_0,
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.get_rptr = vcn_v2_5_dec_ring_get_rptr,
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.get_wptr = vcn_v2_5_dec_ring_get_wptr,
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@ -1786,6 +1786,7 @@ static const struct amdgpu_ring_funcs vcn_v3_0_dec_sw_ring_vm_funcs = {
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.type = AMDGPU_RING_TYPE_VCN_DEC,
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.align_mask = 0x3f,
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.nop = VCN_DEC_SW_CMD_NO_OP,
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.secure_submission_supported = true,
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.vmhub = AMDGPU_MMHUB_0,
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.get_rptr = vcn_v3_0_dec_ring_get_rptr,
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.get_wptr = vcn_v3_0_dec_ring_get_wptr,
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@ -1944,6 +1945,7 @@ static int vcn_v3_0_ring_patch_cs_in_place(struct amdgpu_cs_parser *p,
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static const struct amdgpu_ring_funcs vcn_v3_0_dec_ring_vm_funcs = {
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.type = AMDGPU_RING_TYPE_VCN_DEC,
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.align_mask = 0xf,
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.secure_submission_supported = true,
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.vmhub = AMDGPU_MMHUB_0,
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.get_rptr = vcn_v3_0_dec_ring_get_rptr,
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.get_wptr = vcn_v3_0_dec_ring_get_wptr,
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