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Renesas DTS updates for v6.6 

- Add Clocked Serial Interface (CSI) support for the RZ/V2M SoC,
   - Add PMIC, RTC, and PWM support for the RZ/G2L, RZ/G2LC, and RZ/V2L
     SMARC EVK development boards,
   - Add PWM (MTU3a) support for the RZ/G2UL and RZ/Five SoCs,
   - Add External interrupt (INTC-EX) support for the R-Car S4-8 SoC,
   - Add LED support for the Spider development board,
   - Miscellaneous fixes and improvements.
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Merge tag 'renesas-dts-for-v6.6-tag1' of git://git.kernel.org/pub/scm/linux/kernel/git/geert/renesas-devel into soc/dt

Renesas DTS updates for v6.6

  - Add Clocked Serial Interface (CSI) support for the RZ/V2M SoC,
  - Add PMIC, RTC, and PWM support for the RZ/G2L, RZ/G2LC, and RZ/V2L
    SMARC EVK development boards,
  - Add PWM (MTU3a) support for the RZ/G2UL and RZ/Five SoCs,
  - Add External interrupt (INTC-EX) support for the R-Car S4-8 SoC,
  - Add LED support for the Spider development board,
  - Miscellaneous fixes and improvements.

* tag 'renesas-dts-for-v6.6-tag1' of git://git.kernel.org/pub/scm/linux/kernel/git/geert/renesas-devel:
  arm64: dts: renesas: spider-cpu: Add GP LEDs
  arm64: dts: renesas: r8a779f0: Add INTC-EX node
  arm64: dts: renesas: rzg2ul-smarc: Add support for enabling MTU3
  arm64: dts: renesas: r9a07g043: Add MTU3a node
  ARM dts: renesas: armadillo800eva: Switch to enable-gpios
  arm64: dts: renesas: rzg2lc-smarc-som: Enable PMIC and built-in RTC
  arm64: dts: renesas: rzg2lc-smarc-som: Add PHY interrupt support for ETH0
  riscv: dts: renesas: Clean up dtbs_check W=1 warning due to empty phy node
  arm64: dts: renesas: rzg2lc-smarc: Add support for enabling MTU3
  arm64: dts: renesas: rzg2l-smarc: Add support for enabling MTU3
  arm64: dts: renesas: Add missing space before {
  ARM: dts: renesas: Add missing space before {
  arm64: dts: renesas: Minor whitespace cleanup around '='
  arm64: dts: renesas: rzg2l-smarc-som: Enable PMIC and built-in RTC
  arm64: dts: renesas: r9a09g011: Add CSI nodes
  arm64: dts: renesas: rzg2l: Fix txdv-skew-psec typos
  arm64: dts: renesas: rzg2l: Update overfow/underflow IRQ names for MTU3 channels

Link: https://lore.kernel.org/r/cover.1690545144.git.geert+renesas@glider.be
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
This commit is contained in:
Arnd Bergmann 2023-08-12 10:39:59 +02:00
parent d64f140476 406b5af40e
commit 8be4ee0ee0
26 changed files with 351 additions and 35 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

2
arch/arm/boot/dts/renesas/r8a7740-armadillo800eva.dts
View File

@ -58,7 +58,7 @@
regulator-max-microvolt = <3300000>;
vin-supply = <&vcc_sdhi0>;
enable-gpio = <&pfc 74 GPIO_ACTIVE_HIGH>;
enable-gpios = <&pfc 74 GPIO_ACTIVE_HIGH>;
gpios = <&pfc 17 GPIO_ACTIVE_HIGH>;
states = <3300000 0>, <1800000 1>;

2
arch/arm/boot/dts/renesas/r9a06g032-rzn1d400-db.dts
View File

@ -67,7 +67,7 @@
status = "okay";
};
&pinctrl{
&pinctrl {
pins_can0: pins_can0 {
pinmux = <RZN1_PINMUX(162, RZN1_FUNC_CAN)>, /* CAN0_TXD */
<RZN1_PINMUX(163, RZN1_FUNC_CAN)>; /* CAN0_RXD */

4
arch/arm64/boot/dts/renesas/gmsl-cameras.dtsi
View File

@ -100,7 +100,7 @@
#ifdef GMSL_CAMERA_1
port@1 {
max9286_in1: endpoint{
max9286_in1: endpoint {
remote-endpoint = <&fakra_con1>;
};
@ -233,7 +233,7 @@
#ifdef GMSL_CAMERA_5
port@1 {
max9286_in5: endpoint{
max9286_in5: endpoint {
remote-endpoint = <&fakra_con5>;
};

2
arch/arm64/boot/dts/renesas/r8a77970-v3msk.dts
View File

@ -145,7 +145,7 @@
status = "okay";
clock-frequency = <400000>;
hdmi@39{
hdmi@39 {
compatible = "adi,adv7511w";
#sound-dai-cells = <0>;
reg = <0x39>;

4
arch/arm64/boot/dts/renesas/r8a77990.dtsi
View File

@ -76,7 +76,7 @@
enable-method = "psci";
cpu-idle-states = <&CPU_SLEEP_0>;
dynamic-power-coefficient = <277>;
clocks =<&cpg CPG_CORE R8A77990_CLK_Z2>;
clocks = <&cpg CPG_CORE R8A77990_CLK_Z2>;
operating-points-v2 = <&cluster1_opp>;
};
@ -88,7 +88,7 @@
next-level-cache = <&L2_CA53>;
enable-method = "psci";
cpu-idle-states = <&CPU_SLEEP_0>;
clocks =<&cpg CPG_CORE R8A77990_CLK_Z2>;
clocks = <&cpg CPG_CORE R8A77990_CLK_Z2>;
operating-points-v2 = <&cluster1_opp>;
};

20
arch/arm64/boot/dts/renesas/r8a779f0-spider-cpu.dtsi
View File

@ -6,6 +6,8 @@
*/
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/leds/common.h>
#include "r8a779f0.dtsi"
/ {
@ -22,6 +24,24 @@
stdout-path = "serial0:1843200n8";
};
leds {
compatible = "gpio-leds";
led-7 {
gpios = <&gpio0 11 GPIO_ACTIVE_HIGH>;
color = <LED_COLOR_ID_GREEN>;
function = LED_FUNCTION_INDICATOR;
function-enumerator = <7>;
};
led-8 {
gpios = <&gpio0 14 GPIO_ACTIVE_HIGH>;
color = <LED_COLOR_ID_GREEN>;
function = LED_FUNCTION_INDICATOR;
function-enumerator = <8>;
};
};
memory@48000000 {
device_type = "memory";
/* first 128MB is reserved for secure area. */

15
arch/arm64/boot/dts/renesas/r8a779f0.dtsi
View File

@ -466,6 +466,21 @@
#thermal-sensor-cells = <1>;
};
intc_ex: interrupt-controller@e61c0000 {
compatible = "renesas,intc-ex-r8a779f0", "renesas,irqc";
#interrupt-cells = <2>;
interrupt-controller;
reg = <0 0xe61c0000 0 0x200>;
interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cpg CPG_CORE R8A779F0_CLK_CL16M>;
power-domains = <&sysc R8A779F0_PD_ALWAYS_ON>;
};
tmu0: timer@e61e0000 {
compatible = "renesas,tmu-r8a779f0", "renesas,tmu";
reg = <0 0xe61e0000 0 0x30>;

70
arch/arm64/boot/dts/renesas/r9a07g043.dtsi
View File

@ -74,6 +74,76 @@
#size-cells = <2>;
ranges;
mtu3: timer@10001200 {
compatible = "renesas,r9a07g043-mtu3",
"renesas,rz-mtu3";
reg = <0 0x10001200 0 0xb00>;
interrupts = <SOC_PERIPHERAL_IRQ(170) IRQ_TYPE_EDGE_RISING>,
<SOC_PERIPHERAL_IRQ(171) IRQ_TYPE_EDGE_RISING>,
<SOC_PERIPHERAL_IRQ(172) IRQ_TYPE_EDGE_RISING>,
<SOC_PERIPHERAL_IRQ(173) IRQ_TYPE_EDGE_RISING>,
<SOC_PERIPHERAL_IRQ(174) IRQ_TYPE_EDGE_RISING>,
<SOC_PERIPHERAL_IRQ(175) IRQ_TYPE_EDGE_RISING>,
<SOC_PERIPHERAL_IRQ(176) IRQ_TYPE_EDGE_RISING>,
<SOC_PERIPHERAL_IRQ(177) IRQ_TYPE_EDGE_RISING>,
<SOC_PERIPHERAL_IRQ(178) IRQ_TYPE_EDGE_RISING>,
<SOC_PERIPHERAL_IRQ(179) IRQ_TYPE_EDGE_RISING>,
<SOC_PERIPHERAL_IRQ(180) IRQ_TYPE_EDGE_RISING>,
<SOC_PERIPHERAL_IRQ(181) IRQ_TYPE_EDGE_RISING>,
<SOC_PERIPHERAL_IRQ(182) IRQ_TYPE_EDGE_RISING>,
<SOC_PERIPHERAL_IRQ(183) IRQ_TYPE_EDGE_RISING>,
<SOC_PERIPHERAL_IRQ(184) IRQ_TYPE_EDGE_RISING>,
<SOC_PERIPHERAL_IRQ(185) IRQ_TYPE_EDGE_RISING>,
<SOC_PERIPHERAL_IRQ(186) IRQ_TYPE_EDGE_RISING>,
<SOC_PERIPHERAL_IRQ(187) IRQ_TYPE_EDGE_RISING>,
<SOC_PERIPHERAL_IRQ(188) IRQ_TYPE_EDGE_RISING>,
<SOC_PERIPHERAL_IRQ(189) IRQ_TYPE_EDGE_RISING>,
<SOC_PERIPHERAL_IRQ(190) IRQ_TYPE_EDGE_RISING>,
<SOC_PERIPHERAL_IRQ(191) IRQ_TYPE_EDGE_RISING>,
<SOC_PERIPHERAL_IRQ(192) IRQ_TYPE_EDGE_RISING>,
<SOC_PERIPHERAL_IRQ(193) IRQ_TYPE_EDGE_RISING>,
<SOC_PERIPHERAL_IRQ(194) IRQ_TYPE_EDGE_RISING>,
<SOC_PERIPHERAL_IRQ(195) IRQ_TYPE_EDGE_RISING>,
<SOC_PERIPHERAL_IRQ(196) IRQ_TYPE_EDGE_RISING>,
<SOC_PERIPHERAL_IRQ(197) IRQ_TYPE_EDGE_RISING>,
<SOC_PERIPHERAL_IRQ(198) IRQ_TYPE_EDGE_RISING>,
<SOC_PERIPHERAL_IRQ(199) IRQ_TYPE_EDGE_RISING>,
<SOC_PERIPHERAL_IRQ(200) IRQ_TYPE_EDGE_RISING>,
<SOC_PERIPHERAL_IRQ(201) IRQ_TYPE_EDGE_RISING>,
<SOC_PERIPHERAL_IRQ(202) IRQ_TYPE_EDGE_RISING>,
<SOC_PERIPHERAL_IRQ(203) IRQ_TYPE_EDGE_RISING>,
<SOC_PERIPHERAL_IRQ(204) IRQ_TYPE_EDGE_RISING>,
<SOC_PERIPHERAL_IRQ(205) IRQ_TYPE_EDGE_RISING>,
<SOC_PERIPHERAL_IRQ(206) IRQ_TYPE_EDGE_RISING>,
<SOC_PERIPHERAL_IRQ(207) IRQ_TYPE_EDGE_RISING>,
<SOC_PERIPHERAL_IRQ(208) IRQ_TYPE_EDGE_RISING>,
<SOC_PERIPHERAL_IRQ(209) IRQ_TYPE_EDGE_RISING>,
<SOC_PERIPHERAL_IRQ(210) IRQ_TYPE_EDGE_RISING>,
<SOC_PERIPHERAL_IRQ(211) IRQ_TYPE_EDGE_RISING>,
<SOC_PERIPHERAL_IRQ(212) IRQ_TYPE_EDGE_RISING>,
<SOC_PERIPHERAL_IRQ(213) IRQ_TYPE_EDGE_RISING>;
interrupt-names = "tgia0", "tgib0", "tgic0", "tgid0",
"tciv0", "tgie0", "tgif0",
"tgia1", "tgib1", "tciv1", "tciu1",
"tgia2", "tgib2", "tciv2", "tciu2",
"tgia3", "tgib3", "tgic3", "tgid3",
"tciv3",
"tgia4", "tgib4", "tgic4", "tgid4",
"tciv4",
"tgiu5", "tgiv5", "tgiw5",
"tgia6", "tgib6", "tgic6", "tgid6",
"tciv6",
"tgia7", "tgib7", "tgic7", "tgid7",
"tciv7",
"tgia8", "tgib8", "tgic8", "tgid8",
"tciv8", "tciu8";
clocks = <&cpg CPG_MOD R9A07G043_MTU_X_MCK_MTU3>;
power-domains = <&cpg>;
resets = <&cpg R9A07G043_MTU_X_PRESET_MTU3>;
#pwm-cells = <2>;
status = "disabled";
};
ssi0: ssi@10049c00 {
compatible = "renesas,r9a07g043-ssi",
"renesas,rz-ssi";

11
arch/arm64/boot/dts/renesas/r9a07g043u11-smarc.dts
View File

@ -17,6 +17,17 @@
#define SW_SW0_DEV_SEL 1
#define SW_ET0_EN_N 1
/*
* To enable MTU3a PWM on PMOD0,
* - Set DIP-Switch SW1-3 to On position.
* - Set PMOD_MTU3 macro to 1.
*/
#define PMOD_MTU3 0
#if (PMOD_MTU3 && !SW_ET0_EN_N)
#error "Cannot set as both PMOD_MTU3 and !SW_ET0_EN_N are mutually exclusive"
#endif
#include "r9a07g043u.dtsi"
#include "rzg2ul-smarc-som.dtsi"
#include "rzg2ul-smarc.dtsi"

16
arch/arm64/boot/dts/renesas/r9a07g044.dtsi
View File

@ -223,20 +223,20 @@
<GIC_SPI 212 IRQ_TYPE_EDGE_RISING>,
<GIC_SPI 213 IRQ_TYPE_EDGE_RISING>;
interrupt-names = "tgia0", "tgib0", "tgic0", "tgid0",
"tgiv0", "tgie0", "tgif0",
"tgia1", "tgib1", "tgiv1", "tgiu1",
"tgia2", "tgib2", "tgiv2", "tgiu2",
"tciv0", "tgie0", "tgif0",
"tgia1", "tgib1", "tciv1", "tciu1",
"tgia2", "tgib2", "tciv2", "tciu2",
"tgia3", "tgib3", "tgic3", "tgid3",
"tgiv3",
"tciv3",
"tgia4", "tgib4", "tgic4", "tgid4",
"tgiv4",
"tciv4",
"tgiu5", "tgiv5", "tgiw5",
"tgia6", "tgib6", "tgic6", "tgid6",
"tgiv6",
"tciv6",
"tgia7", "tgib7", "tgic7", "tgid7",
"tgiv7",
"tciv7",
"tgia8", "tgib8", "tgic8", "tgid8",
"tgiv8", "tgiu8";
"tciv8", "tciu8";
clocks = <&cpg CPG_MOD R9A07G044_MTU_X_MCK_MTU3>;
power-domains = <&cpg>;
resets = <&cpg R9A07G044_MTU_X_PRESET_MTU3>;

12
arch/arm64/boot/dts/renesas/r9a07g044c2-smarc.dts
View File

@ -35,6 +35,18 @@
/* comment the #define statement to disable SCIF1 (SER0) on PMOD1 (CN7) */
#define PMOD1_SER0 1
/*
* To enable MTU3a PWM on PMOD0,
* - Set DIP-Switch SW1-4 to Off position.
* - Set SW_RSPI_CAN macro to 0.
* - Set PMOD_MTU3 macro to 1.
*/
#define PMOD_MTU3 0
#if (PMOD_MTU3 && SW_RSPI_CAN)
#error "Cannot set as both PMOD_MTU3 and SW_RSPI_CAN are mutually exclusive"
#endif
#include "r9a07g044c2.dtsi"
#include "rzg2lc-smarc-som.dtsi"
#include "rzg2lc-smarc.dtsi"

21
arch/arm64/boot/dts/renesas/r9a07g044l2-smarc.dts
View File

@ -6,6 +6,27 @@
*/
/dts-v1/;
/* Enable SCIF2 (SER0) on PMOD1 (CN7) */
#define PMOD1_SER0 1
/*
* To enable MTU3a PWM on PMOD0,
* Disable PMOD1_SER0 by setting "#define PMOD1_SER0 0" above and
* enable PMOD_MTU3 by setting "#define PMOD_MTU3 1" below.
*/
#define PMOD_MTU3 0
#if (PMOD_MTU3 && PMOD1_SER0)
#error "Cannot set as PMOD_MTU3 and PMOD1_SER0 are mutually exclusive "
#endif
#define MTU3_COUNTER_Z_PHASE_SIGNAL 0
#if (!PMOD_MTU3 && MTU3_COUNTER_Z_PHASE_SIGNAL)
#error "Cannot set 1 to MTU3_COUNTER_Z_PHASE_SIGNAL as PMOD_MTU3=0"
#endif
#include "r9a07g044l2.dtsi"
#include "rzg2l-smarc-som.dtsi"
#include "rzg2l-smarc-pinfunction.dtsi"

16
arch/arm64/boot/dts/renesas/r9a07g054.dtsi
View File

@ -223,20 +223,20 @@
<GIC_SPI 212 IRQ_TYPE_EDGE_RISING>,
<GIC_SPI 213 IRQ_TYPE_EDGE_RISING>;
interrupt-names = "tgia0", "tgib0", "tgic0", "tgid0",
"tgiv0", "tgie0", "tgif0",
"tgia1", "tgib1", "tgiv1", "tgiu1",
"tgia2", "tgib2", "tgiv2", "tgiu2",
"tciv0", "tgie0", "tgif0",
"tgia1", "tgib1", "tciv1", "tciu1",
"tgia2", "tgib2", "tciv2", "tciu2",
"tgia3", "tgib3", "tgic3", "tgid3",
"tgiv3",
"tciv3",
"tgia4", "tgib4", "tgic4", "tgid4",
"tgiv4",
"tciv4",
"tgiu5", "tgiv5", "tgiw5",
"tgia6", "tgib6", "tgic6", "tgid6",
"tgiv6",
"tciv6",
"tgia7", "tgib7", "tgic7", "tgid7",
"tgiv7",
"tciv7",
"tgia8", "tgib8", "tgic8", "tgid8",
"tgiv8", "tgiu8";
"tciv8", "tciu8";
clocks = <&cpg CPG_MOD R9A07G054_MTU_X_MCK_MTU3>;
power-domains = <&cpg>;
resets = <&cpg R9A07G054_MTU_X_PRESET_MTU3>;

20
arch/arm64/boot/dts/renesas/r9a07g054l2-smarc.dts
View File

@ -6,6 +6,26 @@
*/
/dts-v1/;
/* Enable SCIF2 (SER0) on PMOD1 (CN7) */
#define PMOD1_SER0 1
/*
* To enable MTU3a PWM on PMOD0,
* Disable PMOD1_SER0 by setting "#define PMOD1_SER0 0" above and
* enable PMOD_MTU3 by setting "#define PMOD_MTU3 1" below.
*/
#define PMOD_MTU3 0
#if (PMOD_MTU3 && PMOD1_SER0)
#error "Cannot set as PMOD_MTU3 and PMOD1_SER0 are mutually exclusive "
#endif
#define MTU3_COUNTER_Z_PHASE_SIGNAL 0
#if (!PMOD_MTU3 && MTU3_COUNTER_Z_PHASE_SIGNAL)
#error "Cannot set 1 to MTU3_COUNTER_Z_PHASE_SIGNAL as PMOD_MTU3=0"
#endif
#include "r9a07g054l2.dtsi"
#include "rzg2l-smarc-som.dtsi"
#include "rzg2l-smarc-pinfunction.dtsi"

28
arch/arm64/boot/dts/renesas/r9a09g011.dtsi
View File

@ -236,6 +236,34 @@
reg = <0 0xa3f03000 0 0x400>;
};
csi0: spi@a4020000 {
compatible = "renesas,rzv2m-csi";
reg = <0 0xa4020000 0 0x80>;
interrupts = <GIC_SPI 226 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cpg CPG_MOD R9A09G011_CSI0_CLK>,
<&cpg CPG_MOD R9A09G011_CPERI_GRPG_PCLK>;
clock-names = "csiclk", "pclk";
resets = <&cpg R9A09G011_CSI_GPG_PRESETN>;
power-domains = <&cpg>;
#address-cells = <1>;
#size-cells = <0>;
status = "disabled";
};
csi4: spi@a4020200 {
compatible = "renesas,rzv2m-csi";
reg = <0 0xa4020200 0 0x80>;
interrupts = <GIC_SPI 230 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cpg CPG_MOD R9A09G011_CSI4_CLK>,
<&cpg CPG_MOD R9A09G011_CPERI_GRPH_PCLK>;
clock-names = "csiclk", "pclk";
resets = <&cpg R9A09G011_CSI_GPH_PRESETN>;
power-domains = <&cpg>;
#address-cells = <1>;
#size-cells = <0>;
status = "disabled";
};
i2c0: i2c@a4030000 {
#address-cells = <1>;
#size-cells = <0>;

4
arch/arm64/boot/dts/renesas/rz-smarc-common.dtsi
View File

@ -78,11 +78,11 @@
};
};
&audio_clk1{
&audio_clk1 {
clock-frequency = <11289600>;
};
&audio_clk2{
&audio_clk2 {
clock-frequency = <12288000>;
};

20
arch/arm64/boot/dts/renesas/rzg2l-smarc-pinfunction.dtsi
View File

@ -53,6 +53,26 @@
<RZG2L_PORT_PINMUX(18, 1, 3)>; /* SCL */
};
mtu3_pins: mtu3 {
mtu3-ext-clk-input-pin {
pinmux = <RZG2L_PORT_PINMUX(48, 0, 4)>, /* MTCLKA */
<RZG2L_PORT_PINMUX(48, 1, 4)>; /* MTCLKB */
};
mtu3-pwm {
pinmux = <RZG2L_PORT_PINMUX(44, 0, 4)>, /* MTIOC3A */
<RZG2L_PORT_PINMUX(44, 1, 4)>, /* MTIOC3B */
<RZG2L_PORT_PINMUX(44, 2, 4)>, /* MTIOC3C */
<RZG2L_PORT_PINMUX(44, 3, 4)>; /* MTIOC3D */
};
#if MTU3_COUNTER_Z_PHASE_SIGNAL
mtu3-zphase-clk {
pinmux = <RZG2L_PORT_PINMUX(19, 0, 3)>; /* MTIOC1A */
};
#endif /* MTU3_COUNTER_Z_PHASE_SIGNAL */
};
scif0_pins: scif0 {
pinmux = <RZG2L_PORT_PINMUX(38, 0, 1)>, /* TxD */
<RZG2L_PORT_PINMUX(38, 1, 1)>; /* RxD */

22
arch/arm64/boot/dts/renesas/rzg2l-smarc-som.dtsi
View File

@ -73,6 +73,13 @@
gpios = <&pinctrl RZG2L_GPIO(39, 0) GPIO_ACTIVE_HIGH>;
regulator-always-on;
};
/* 32.768kHz crystal */
x2: x2-clock {
compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency = <32768>;
};
};
&adc {
@ -100,7 +107,7 @@
rxc-skew-psec = <2400>;
txc-skew-psec = <2400>;
rxdv-skew-psec = <0>;
txdv-skew-psec = <0>;
txen-skew-psec = <0>;
rxd0-skew-psec = <0>;
rxd1-skew-psec = <0>;
rxd2-skew-psec = <0>;
@ -128,7 +135,7 @@
rxc-skew-psec = <2400>;
txc-skew-psec = <2400>;
rxdv-skew-psec = <0>;
txdv-skew-psec = <0>;
txen-skew-psec = <0>;
rxd0-skew-psec = <0>;
rxd1-skew-psec = <0>;
rxd2-skew-psec = <0>;
@ -148,6 +155,17 @@
mali-supply = <&reg_1p1v>;
};
&i2c3 {
raa215300: pmic@12 {
compatible = "renesas,raa215300";
reg = <0x12>, <0x6f>;
reg-names = "main", "rtc";
clocks = <&x2>;
clock-names = "xin";
};
};
&ostm1 {
status = "okay";
};

23
arch/arm64/boot/dts/renesas/rzg2l-smarc.dtsi
View File

@ -8,9 +8,6 @@
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/pinctrl/rzg2l-pinctrl.h>
/* comment the #define statement to disable SCIF2 (SER0) on PMOD1 (CN7) */
#define PMOD1_SER0 1
/ {
aliases {
serial1 = &scif2;
@ -115,6 +112,26 @@
};
};
#if PMOD_MTU3
&mtu3 {
pinctrl-0 = <&mtu3_pins>;
pinctrl-names = "default";
status = "okay";
};
#if MTU3_COUNTER_Z_PHASE_SIGNAL
/* SDHI cd pin is muxed with counter Z phase signal */
&sdhi1 {
status = "disabled";
};
#endif /* MTU3_COUNTER_Z_PHASE_SIGNAL */
&spi1 {
status = "disabled";
};
#endif /* PMOD_MTU3 */
/*
* To enable SCIF2 (SER0) on PMOD1 (CN7)
* SW1 should be at position 2->3 so that SER0_CTS# line is activated

9
arch/arm64/boot/dts/renesas/rzg2lc-smarc-pinfunction.dtsi
View File

@ -50,6 +50,15 @@
<RZG2L_PORT_PINMUX(42, 4, 1)>; /* SCL */
};
mtu3_pins: mtu3 {
mtu3-pwm {
pinmux = <RZG2L_PORT_PINMUX(44, 0, 4)>, /* MTIOC3A */
<RZG2L_PORT_PINMUX(44, 1, 4)>, /* MTIOC3B */
<RZG2L_PORT_PINMUX(44, 2, 4)>, /* MTIOC3C */
<RZG2L_PORT_PINMUX(44, 3, 4)>; /* MTIOC3D */
};
};
scif0_pins: scif0 {
pinmux = <RZG2L_PORT_PINMUX(38, 0, 1)>, /* TxD */
<RZG2L_PORT_PINMUX(38, 1, 1)>; /* RxD */

26
arch/arm64/boot/dts/renesas/rzg2lc-smarc-som.dtsi
View File

@ -6,6 +6,7 @@
*/
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/interrupt-controller/irqc-rzg2l.h>
#include <dt-bindings/pinctrl/rzg2l-pinctrl.h>
/ {
@ -61,6 +62,13 @@
gpios = <&pinctrl RZG2L_GPIO(39, 0) GPIO_ACTIVE_HIGH>;
regulator-always-on;
};
/* 32.768kHz crystal */
x2: x2-clock {
compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency = <32768>;
};
};
&eth0 {
@ -74,10 +82,12 @@
compatible = "ethernet-phy-id0022.1640",
"ethernet-phy-ieee802.3-c22";
reg = <7>;
interrupt-parent = <&irqc>;
interrupts = <RZG2L_IRQ0 IRQ_TYPE_LEVEL_LOW>;
rxc-skew-psec = <2400>;
txc-skew-psec = <2400>;
rxdv-skew-psec = <0>;
txdv-skew-psec = <0>;
txen-skew-psec = <0>;
rxd0-skew-psec = <0>;
rxd1-skew-psec = <0>;
rxd2-skew-psec = <0>;
@ -97,6 +107,17 @@
mali-supply = <&reg_1p1v>;
};
&i2c2 {
raa215300: pmic@12 {
compatible = "renesas,raa215300";
reg = <0x12>, <0x6f>;
reg-names = "main", "rtc";
clocks = <&x2>;
clock-names = "xin";
};
};
&ostm1 {
status = "okay";
};
@ -121,7 +142,8 @@
<RZG2L_PORT_PINMUX(25, 0, 1)>, /* ET0_RXD0 */
<RZG2L_PORT_PINMUX(25, 1, 1)>, /* ET0_RXD1 */
<RZG2L_PORT_PINMUX(26, 0, 1)>, /* ET0_RXD2 */
<RZG2L_PORT_PINMUX(26, 1, 1)>; /* ET0_RXD3 */
<RZG2L_PORT_PINMUX(26, 1, 1)>, /* ET0_RXD3 */
<RZG2L_PORT_PINMUX(0, 0, 1)>; /* IRQ0 */
};
gpio-sd0-pwr-en-hog {

14
arch/arm64/boot/dts/renesas/rzg2lc-smarc.dtsi
View File

@ -11,7 +11,6 @@
#include "rzg2lc-smarc-pinfunction.dtsi"
#include "rz-smarc-common.dtsi"
/ {
aliases {
serial1 = &scif1;
@ -129,6 +128,19 @@
};
};
#if PMOD_MTU3
&mtu3 {
pinctrl-0 = <&mtu3_pins>;
pinctrl-names = "default";
status = "okay";
};
&spi1 {
status = "disabled";
};
#endif
/*
* To enable SCIF1 (SER0) on PMOD1 (CN7), On connector board
* SW1 should be at position 2->3 so that SER0_CTS# line is activated

6
arch/arm64/boot/dts/renesas/rzg2ul-smarc-pinfunction.dtsi
View File

@ -50,6 +50,12 @@
input-enable;
};
mtu3_pins: mtu3 {
mtu2-pwm {
pinmux = <RZG2L_PORT_PINMUX(4, 0, 4)>; /* MTIOC2A */
};
};
scif0_pins: scif0 {
pinmux = <RZG2L_PORT_PINMUX(6, 4, 6)>, /* TxD */
<RZG2L_PORT_PINMUX(6, 3, 6)>; /* RxD */

4
arch/arm64/boot/dts/renesas/rzg2ul-smarc-som.dtsi
View File

@ -83,7 +83,7 @@
rxc-skew-psec = <2400>;
txc-skew-psec = <2400>;
rxdv-skew-psec = <0>;
txdv-skew-psec = <0>;
txen-skew-psec = <0>;
rxd0-skew-psec = <0>;
rxd1-skew-psec = <0>;
rxd2-skew-psec = <0>;
@ -112,7 +112,7 @@
rxc-skew-psec = <2400>;
txc-skew-psec = <2400>;
rxdv-skew-psec = <0>;
txdv-skew-psec = <0>;
txen-skew-psec = <0>;
rxd0-skew-psec = <0>;
rxd1-skew-psec = <0>;
rxd2-skew-psec = <0>;

13
arch/arm64/boot/dts/renesas/rzg2ul-smarc.dtsi
View File

@ -28,6 +28,19 @@
};
};
#if PMOD_MTU3
&mtu3 {
pinctrl-0 = <&mtu3_pins>;
pinctrl-names = "default";
status = "okay";
};
&spi1 {
status = "disabled";
};
#endif
#if (SW_ET0_EN_N)
&ssi1 {
pinctrl-0 = <&ssi1_pins>;

2
arch/riscv/boot/dts/renesas/rzfive-smarc-som.dtsi
View File

@ -22,6 +22,7 @@
status = "disabled";
};
#if (!SW_ET0_EN_N)
&eth0 {
status = "disabled";
@ -30,6 +31,7 @@
/delete-property/ interrupts;
};
};
#endif
&eth1 {
status = "disabled";