Merge branch 'fixes' of http://ftp.arm.linux.org.uk/pub/linux/arm/kernel/git-cur/linux-2.6-arm
* 'fixes' of http://ftp.arm.linux.org.uk/pub/linux/arm/kernel/git-cur/linux-2.6-arm: ARM: 7128/1: vic: Don't write to the read-only register VIC_IRQ_STATUS ARM: 7122/1: localtimer: add header linux/errno.h explicitly ARM: 7117/1: perf: fix HW_CACHE_* events on Cortex-A9 ARM: 7113/1: mm: Align bank start to MAX_ORDER_NR_PAGES
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commit
8bc03e8f3a
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@ -259,7 +259,6 @@ static void __init vic_disable(void __iomem *base)
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writel(0, base + VIC_INT_SELECT);
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writel(0, base + VIC_INT_ENABLE);
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writel(~0, base + VIC_INT_ENABLE_CLEAR);
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writel(0, base + VIC_IRQ_STATUS);
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writel(0, base + VIC_ITCR);
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writel(~0, base + VIC_INT_SOFT_CLEAR);
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}
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@ -10,6 +10,8 @@
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#ifndef __ASM_ARM_LOCALTIMER_H
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#define __ASM_ARM_LOCALTIMER_H
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#include <linux/errno.h>
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struct clock_event_device;
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/*
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@ -321,8 +321,8 @@ static const unsigned armv7_a9_perf_map[PERF_COUNT_HW_MAX] = {
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[PERF_COUNT_HW_CPU_CYCLES] = ARMV7_PERFCTR_CPU_CYCLES,
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[PERF_COUNT_HW_INSTRUCTIONS] =
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ARMV7_PERFCTR_INST_OUT_OF_RENAME_STAGE,
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[PERF_COUNT_HW_CACHE_REFERENCES] = ARMV7_PERFCTR_COHERENT_LINE_HIT,
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[PERF_COUNT_HW_CACHE_MISSES] = ARMV7_PERFCTR_COHERENT_LINE_MISS,
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[PERF_COUNT_HW_CACHE_REFERENCES] = ARMV7_PERFCTR_DCACHE_ACCESS,
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[PERF_COUNT_HW_CACHE_MISSES] = ARMV7_PERFCTR_DCACHE_REFILL,
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[PERF_COUNT_HW_BRANCH_INSTRUCTIONS] = ARMV7_PERFCTR_PC_WRITE,
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[PERF_COUNT_HW_BRANCH_MISSES] = ARMV7_PERFCTR_PC_BRANCH_MIS_PRED,
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[PERF_COUNT_HW_BUS_CYCLES] = ARMV7_PERFCTR_CLOCK_CYCLES,
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@ -496,6 +496,13 @@ static void __init free_unused_memmap(struct meminfo *mi)
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*/
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bank_start = min(bank_start,
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ALIGN(prev_bank_end, PAGES_PER_SECTION));
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#else
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/*
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* Align down here since the VM subsystem insists that the
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* memmap entries are valid from the bank start aligned to
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* MAX_ORDER_NR_PAGES.
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*/
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bank_start = round_down(bank_start, MAX_ORDER_NR_PAGES);
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#endif
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/*
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* If we had a previous bank, and there is a space
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