ARM: dts: uniphier: Add USB2 PHY nodes
Add nodes of USB2 physical layer for UniPhier SoC. This supports Pro4. Signed-off-by: Kunihiko Hayashi <hayashi.kunihiko@socionext.com> Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
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@ -328,6 +328,8 @@
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<&mio_clk 12>;
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resets = <&sys_rst 8>, <&mio_rst 7>, <&mio_rst 8>,
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<&mio_rst 12>;
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phy-names = "usb";
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phys = <&usb_phy0>;
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has-transaction-translator;
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};
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@ -342,6 +344,8 @@
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<&mio_clk 13>;
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resets = <&sys_rst 8>, <&mio_rst 7>, <&mio_rst 9>,
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<&mio_rst 13>;
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phy-names = "usb";
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phys = <&usb_phy1>;
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has-transaction-translator;
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};
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@ -353,6 +357,34 @@
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pinctrl: pinctrl {
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compatible = "socionext,uniphier-pro4-pinctrl";
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};
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usb-phy {
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compatible = "socionext,uniphier-pro4-usb2-phy";
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#address-cells = <1>;
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#size-cells = <0>;
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usb_phy0: phy@0 {
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reg = <0>;
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#phy-cells = <0>;
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};
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usb_phy1: phy@1 {
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reg = <1>;
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#phy-cells = <0>;
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};
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usb_phy2: phy@2 {
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reg = <2>;
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#phy-cells = <0>;
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vbus-supply = <&usb0_vbus>;
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};
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usb_phy3: phy@3 {
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reg = <3>;
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#phy-cells = <0>;
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vbus-supply = <&usb1_vbus>;
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};
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};
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};
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soc-glue@5f900000 {
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@ -456,7 +488,7 @@
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clock-names = "ref", "bus_early", "suspend";
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clocks = <&sys_clk 12>, <&sys_clk 12>, <&sys_clk 12>;
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resets = <&usb0_rst 4>;
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phys = <&usb0_ssphy>;
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phys = <&usb_phy2>, <&usb0_ssphy>;
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dr_mode = "host";
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};
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@ -509,6 +541,7 @@
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clock-names = "ref", "bus_early", "suspend";
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clocks = <&sys_clk 12>, <&sys_clk 12>, <&sys_clk 12>;
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resets = <&usb1_rst 4>;
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phys = <&usb_phy3>;
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dr_mode = "host";
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};
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