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drm/i915: restore fixed FDI link rate on Sandybridge 

FDI_PLL_BIOS_0 register is for Ironlake only, don't apply to
Sandybridge.

Original-patch-by: Zhenyu Wang <zhenyuw@linux.intel.com>
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
This commit is contained in:
Chris Wilson 2010-10-13 09:59:17 +01:00
parent 736085bcf9
commit 8b99e68c0a
1 changed files with 5 additions and 2 deletions
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7
drivers/gpu/drm/i915/intel_display.c
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@ -345,8 +345,11 @@ intel_find_pll_ironlake_dp(const intel_limit_t *, struct drm_crtc *crtc,
static inline u32 /* units of 100MHz */ static inline u32 /* units of 100MHz */
intel_fdi_link_freq(struct drm_device *dev) intel_fdi_link_freq(struct drm_device *dev)
{ {
struct drm_i915_private *dev_priv = dev->dev_private; if (IS_GEN5(dev)) {
return (I915_READ(FDI_PLL_BIOS_0) & FDI_PLL_FB_CLOCK_MASK) + 2; struct drm_i915_private *dev_priv = dev->dev_private;
return (I915_READ(FDI_PLL_BIOS_0) & FDI_PLL_FB_CLOCK_MASK) + 2;
} else
return 27;
} }
static const intel_limit_t intel_limits_i8xx_dvo = { static const intel_limit_t intel_limits_i8xx_dvo = {