drm/amdgpu: indirect register access for nv12 sriov
unify host driver and guest driver indirect access control bits names Signed-off-by: Peng Ju Zhou <PengJu.Zhou@amd.com> Reviewed-by: Emily.Deng <Emily.Deng@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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@ -110,11 +110,11 @@ enum AMDGIM_FEATURE_FLAG {
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enum AMDGIM_REG_ACCESS_FLAG {
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/* Use PSP to program IH_RB_CNTL */
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AMDGIM_FEATURE_IH_REG_PSP_EN = (1 << 0),
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AMDGIM_FEATURE_IH_REG_PSP_EN = (1 << 0),
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/* Use RLC to program MMHUB regs */
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AMDGIM_FEATURE_RLC_MMHUB_EN = (1 << 1),
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AMDGIM_FEATURE_MMHUB_REG_RLC_EN = (1 << 1),
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/* Use RLC to program GC regs */
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AMDGIM_FEATURE_RLC_GC_EN = (1 << 2),
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AMDGIM_FEATURE_GC_REG_RLC_EN = (1 << 2),
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};
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struct amdgim_pf2vf_info_v1 {
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