ARM: 7615/1: cache-l2x0: aurora: Invalidate during clean operation with WT enable
This patch fixes a bug for Aurora L2 cache controller when the write-through mode is enable. For the clean operation even if we don't have to flush the lines we still need to invalidate them. Signed-off-by: Gregory CLEMENT <gregory.clement@free-electrons.com> Tested-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com> Acked-by: Jason Cooper <jason@lakedaemon.net> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
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@ -506,15 +506,21 @@ static void aurora_clean_range(unsigned long start, unsigned long end)
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static void aurora_flush_range(unsigned long start, unsigned long end)
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static void aurora_flush_range(unsigned long start, unsigned long end)
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{
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{
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if (!l2_wt_override) {
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start &= ~(CACHE_LINE_SIZE - 1);
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start &= ~(CACHE_LINE_SIZE - 1);
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end = ALIGN(end, CACHE_LINE_SIZE);
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end = ALIGN(end, CACHE_LINE_SIZE);
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while (start != end) {
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while (start != end) {
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unsigned long range_end = calc_range_end(start, end);
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unsigned long range_end = calc_range_end(start, end);
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/*
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* If L2 is forced to WT, the L2 will always be clean and we
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* just need to invalidate.
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*/
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if (l2_wt_override)
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aurora_pa_range(start, range_end - CACHE_LINE_SIZE,
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aurora_pa_range(start, range_end - CACHE_LINE_SIZE,
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AURORA_FLUSH_RANGE_REG);
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AURORA_INVAL_RANGE_REG);
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start = range_end;
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else
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}
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aurora_pa_range(start, range_end - CACHE_LINE_SIZE,
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AURORA_FLUSH_RANGE_REG);
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start = range_end;
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}
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}
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}
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}
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