gpio: ep93xx: fix BUG_ON port F usage
Two index spaces and ep93xx_gpio_port are confusing.
Instead add a separate struct to store necessary data and remove
ep93xx_gpio_port.
- add struct to store IRQ related data for each IRQ capable chip
- replace offset array with defined offsets
- add IRQ registers offset for each IRQ capable chip into
ep93xx_gpio_banks
------------[ cut here ]------------
kernel BUG at drivers/gpio/gpio-ep93xx.c:64!
---[ end trace 3f6544e133e9f5ae ]---
Fixes: fd935fc421 ("gpio: ep93xx: Do not pingpong irq numbers")
Cc: <stable@vger.kernel.org>
Reviewed-by: Alexander Sverdlin <alexander.sverdlin@gmail.com>
Tested-by: Alexander Sverdlin <alexander.sverdlin@gmail.com>
Signed-off-by: Nikita Shubin <nikita.shubin@maquefel.me>
Signed-off-by: Bartosz Golaszewski <bgolaszewski@baylibre.com>
This commit is contained in:
Nikita Shubin
Bartosz Golaszewski
parent
97c6e28d38
commit
8b81a7ab80
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@ -25,6 +25,9 @@
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/* Maximum value for gpio line identifiers */
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#define EP93XX_GPIO_LINE_MAX 63
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/* Number of GPIO chips in EP93XX */
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#define EP93XX_GPIO_CHIP_NUM 8
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/* Maximum value for irq capable line identifiers */
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#define EP93XX_GPIO_LINE_MAX_IRQ 23
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@ -34,74 +37,74 @@
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*/
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#define EP93XX_GPIO_F_IRQ_BASE 80
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struct ep93xx_gpio_irq_chip {
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u8 irq_offset;
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u8 int_unmasked;
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u8 int_enabled;
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u8 int_type1;
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u8 int_type2;
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u8 int_debounce;
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};
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struct ep93xx_gpio_chip {
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struct gpio_chip gc;
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struct ep93xx_gpio_irq_chip *eic;
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};
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struct ep93xx_gpio {
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void __iomem *base;
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struct gpio_chip gc[8];
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struct ep93xx_gpio_chip gc[EP93XX_GPIO_CHIP_NUM];
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};
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#define to_ep93xx_gpio_chip(x) container_of(x, struct ep93xx_gpio_chip, gc)
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static struct ep93xx_gpio_irq_chip *to_ep93xx_gpio_irq_chip(struct gpio_chip *gc)
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{
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struct ep93xx_gpio_chip *egc = to_ep93xx_gpio_chip(gc);
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return egc->eic;
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}
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/*************************************************************************
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* Interrupt handling for EP93xx on-chip GPIOs
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*************************************************************************/
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static unsigned char gpio_int_unmasked[3];
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static unsigned char gpio_int_enabled[3];
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static unsigned char gpio_int_type1[3];
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static unsigned char gpio_int_type2[3];
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static unsigned char gpio_int_debounce[3];
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#define EP93XX_INT_TYPE1_OFFSET 0x00
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#define EP93XX_INT_TYPE2_OFFSET 0x04
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#define EP93XX_INT_EOI_OFFSET 0x08
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#define EP93XX_INT_EN_OFFSET 0x0c
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#define EP93XX_INT_STATUS_OFFSET 0x10
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#define EP93XX_INT_RAW_STATUS_OFFSET 0x14
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#define EP93XX_INT_DEBOUNCE_OFFSET 0x18
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/* Port ordering is: A B F */
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static const u8 int_type1_register_offset[3] = { 0x90, 0xac, 0x4c };
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static const u8 int_type2_register_offset[3] = { 0x94, 0xb0, 0x50 };
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static const u8 eoi_register_offset[3] = { 0x98, 0xb4, 0x54 };
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static const u8 int_en_register_offset[3] = { 0x9c, 0xb8, 0x58 };
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static const u8 int_debounce_register_offset[3] = { 0xa8, 0xc4, 0x64 };
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static void ep93xx_gpio_update_int_params(struct ep93xx_gpio *epg, unsigned port)
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static void ep93xx_gpio_update_int_params(struct ep93xx_gpio *epg,
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struct ep93xx_gpio_irq_chip *eic)
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{
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BUG_ON(port > 2);
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writeb_relaxed(0, epg->base + eic->irq_offset + EP93XX_INT_EN_OFFSET);
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writeb_relaxed(0, epg->base + int_en_register_offset[port]);
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writeb_relaxed(eic->int_type2,
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epg->base + eic->irq_offset + EP93XX_INT_TYPE2_OFFSET);
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writeb_relaxed(gpio_int_type2[port],
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epg->base + int_type2_register_offset[port]);
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writeb_relaxed(eic->int_type1,
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epg->base + eic->irq_offset + EP93XX_INT_TYPE1_OFFSET);
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writeb_relaxed(gpio_int_type1[port],
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epg->base + int_type1_register_offset[port]);
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writeb(gpio_int_unmasked[port] & gpio_int_enabled[port],
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epg->base + int_en_register_offset[port]);
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}
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static int ep93xx_gpio_port(struct gpio_chip *gc)
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{
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struct ep93xx_gpio *epg = gpiochip_get_data(gc);
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int port = 0;
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while (port < ARRAY_SIZE(epg->gc) && gc != &epg->gc[port])
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port++;
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/* This should not happen but is there as a last safeguard */
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if (port == ARRAY_SIZE(epg->gc)) {
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pr_crit("can't find the GPIO port\n");
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return 0;
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}
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return port;
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writeb_relaxed(eic->int_unmasked & eic->int_enabled,
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epg->base + eic->irq_offset + EP93XX_INT_EN_OFFSET);
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}
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static void ep93xx_gpio_int_debounce(struct gpio_chip *gc,
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unsigned int offset, bool enable)
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{
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struct ep93xx_gpio *epg = gpiochip_get_data(gc);
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int port = ep93xx_gpio_port(gc);
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struct ep93xx_gpio_irq_chip *eic = to_ep93xx_gpio_irq_chip(gc);
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int port_mask = BIT(offset);
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if (enable)
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gpio_int_debounce[port] |= port_mask;
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eic->int_debounce |= port_mask;
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else
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gpio_int_debounce[port] &= ~port_mask;
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eic->int_debounce &= ~port_mask;
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writeb(gpio_int_debounce[port],
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epg->base + int_debounce_register_offset[port]);
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writeb(eic->int_debounce,
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epg->base + eic->irq_offset + EP93XX_INT_DEBOUNCE_OFFSET);
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}
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static void ep93xx_gpio_ab_irq_handler(struct irq_desc *desc)
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@ -122,12 +125,12 @@ static void ep93xx_gpio_ab_irq_handler(struct irq_desc *desc)
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*/
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stat = readb(epg->base + EP93XX_GPIO_A_INT_STATUS);
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for_each_set_bit(offset, &stat, 8)
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generic_handle_irq(irq_find_mapping(epg->gc[0].irq.domain,
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generic_handle_irq(irq_find_mapping(epg->gc[0].gc.irq.domain,
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offset));
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stat = readb(epg->base + EP93XX_GPIO_B_INT_STATUS);
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for_each_set_bit(offset, &stat, 8)
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generic_handle_irq(irq_find_mapping(epg->gc[1].irq.domain,
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generic_handle_irq(irq_find_mapping(epg->gc[1].gc.irq.domain,
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offset));
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chained_irq_exit(irqchip, desc);
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@ -153,52 +156,52 @@ static void ep93xx_gpio_f_irq_handler(struct irq_desc *desc)
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static void ep93xx_gpio_irq_ack(struct irq_data *d)
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{
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struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
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struct ep93xx_gpio_irq_chip *eic = to_ep93xx_gpio_irq_chip(gc);
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struct ep93xx_gpio *epg = gpiochip_get_data(gc);
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int port = ep93xx_gpio_port(gc);
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int port_mask = BIT(d->irq & 7);
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if (irqd_get_trigger_type(d) == IRQ_TYPE_EDGE_BOTH) {
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gpio_int_type2[port] ^= port_mask; /* switch edge direction */
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ep93xx_gpio_update_int_params(epg, port);
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eic->int_type2 ^= port_mask; /* switch edge direction */
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ep93xx_gpio_update_int_params(epg, eic);
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}
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writeb(port_mask, epg->base + eoi_register_offset[port]);
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writeb(port_mask, epg->base + eic->irq_offset + EP93XX_INT_EOI_OFFSET);
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}
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static void ep93xx_gpio_irq_mask_ack(struct irq_data *d)
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{
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struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
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struct ep93xx_gpio_irq_chip *eic = to_ep93xx_gpio_irq_chip(gc);
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struct ep93xx_gpio *epg = gpiochip_get_data(gc);
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int port = ep93xx_gpio_port(gc);
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int port_mask = BIT(d->irq & 7);
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if (irqd_get_trigger_type(d) == IRQ_TYPE_EDGE_BOTH)
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gpio_int_type2[port] ^= port_mask; /* switch edge direction */
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eic->int_type2 ^= port_mask; /* switch edge direction */
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gpio_int_unmasked[port] &= ~port_mask;
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ep93xx_gpio_update_int_params(epg, port);
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eic->int_unmasked &= ~port_mask;
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ep93xx_gpio_update_int_params(epg, eic);
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writeb(port_mask, epg->base + eoi_register_offset[port]);
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writeb(port_mask, epg->base + eic->irq_offset + EP93XX_INT_EOI_OFFSET);
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}
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static void ep93xx_gpio_irq_mask(struct irq_data *d)
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{
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struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
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struct ep93xx_gpio_irq_chip *eic = to_ep93xx_gpio_irq_chip(gc);
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struct ep93xx_gpio *epg = gpiochip_get_data(gc);
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int port = ep93xx_gpio_port(gc);
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gpio_int_unmasked[port] &= ~BIT(d->irq & 7);
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ep93xx_gpio_update_int_params(epg, port);
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eic->int_unmasked &= ~BIT(d->irq & 7);
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ep93xx_gpio_update_int_params(epg, eic);
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}
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static void ep93xx_gpio_irq_unmask(struct irq_data *d)
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{
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struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
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struct ep93xx_gpio_irq_chip *eic = to_ep93xx_gpio_irq_chip(gc);
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struct ep93xx_gpio *epg = gpiochip_get_data(gc);
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int port = ep93xx_gpio_port(gc);
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gpio_int_unmasked[port] |= BIT(d->irq & 7);
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ep93xx_gpio_update_int_params(epg, port);
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eic->int_unmasked |= BIT(d->irq & 7);
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ep93xx_gpio_update_int_params(epg, eic);
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}
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/*
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@ -209,8 +212,8 @@ static void ep93xx_gpio_irq_unmask(struct irq_data *d)
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static int ep93xx_gpio_irq_type(struct irq_data *d, unsigned int type)
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{
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struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
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struct ep93xx_gpio_irq_chip *eic = to_ep93xx_gpio_irq_chip(gc);
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struct ep93xx_gpio *epg = gpiochip_get_data(gc);
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int port = ep93xx_gpio_port(gc);
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int offset = d->irq & 7;
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int port_mask = BIT(offset);
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irq_flow_handler_t handler;
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@ -219,32 +222,32 @@ static int ep93xx_gpio_irq_type(struct irq_data *d, unsigned int type)
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switch (type) {
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case IRQ_TYPE_EDGE_RISING:
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gpio_int_type1[port] |= port_mask;
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gpio_int_type2[port] |= port_mask;
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eic->int_type1 |= port_mask;
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eic->int_type2 |= port_mask;
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handler = handle_edge_irq;
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break;
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case IRQ_TYPE_EDGE_FALLING:
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gpio_int_type1[port] |= port_mask;
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gpio_int_type2[port] &= ~port_mask;
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eic->int_type1 |= port_mask;
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eic->int_type2 &= ~port_mask;
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handler = handle_edge_irq;
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break;
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case IRQ_TYPE_LEVEL_HIGH:
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gpio_int_type1[port] &= ~port_mask;
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gpio_int_type2[port] |= port_mask;
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eic->int_type1 &= ~port_mask;
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eic->int_type2 |= port_mask;
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handler = handle_level_irq;
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break;
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case IRQ_TYPE_LEVEL_LOW:
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gpio_int_type1[port] &= ~port_mask;
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gpio_int_type2[port] &= ~port_mask;
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eic->int_type1 &= ~port_mask;
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eic->int_type2 &= ~port_mask;
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handler = handle_level_irq;
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break;
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case IRQ_TYPE_EDGE_BOTH:
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gpio_int_type1[port] |= port_mask;
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eic->int_type1 |= port_mask;
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/* set initial polarity based on current input level */
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if (gc->get(gc, offset))
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gpio_int_type2[port] &= ~port_mask; /* falling */
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eic->int_type2 &= ~port_mask; /* falling */
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else
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gpio_int_type2[port] |= port_mask; /* rising */
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eic->int_type2 |= port_mask; /* rising */
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handler = handle_edge_irq;
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break;
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default:
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@ -253,9 +256,9 @@ static int ep93xx_gpio_irq_type(struct irq_data *d, unsigned int type)
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irq_set_handler_locked(d, handler);
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gpio_int_enabled[port] |= port_mask;
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eic->int_enabled |= port_mask;
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ep93xx_gpio_update_int_params(epg, port);
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ep93xx_gpio_update_int_params(epg, eic);
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return 0;
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}
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@ -276,17 +279,19 @@ struct ep93xx_gpio_bank {
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const char *label;
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int data;
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int dir;
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int irq;
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int base;
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bool has_irq;
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bool has_hierarchical_irq;
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unsigned int irq_base;
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};
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#define EP93XX_GPIO_BANK(_label, _data, _dir, _base, _has_irq, _has_hier, _irq_base) \
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#define EP93XX_GPIO_BANK(_label, _data, _dir, _irq, _base, _has_irq, _has_hier, _irq_base) \
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{ \
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.label = _label, \
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.data = _data, \
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.dir = _dir, \
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.irq = _irq, \
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.base = _base, \
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.has_irq = _has_irq, \
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.has_hierarchical_irq = _has_hier, \
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@ -295,16 +300,16 @@ struct ep93xx_gpio_bank {
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static struct ep93xx_gpio_bank ep93xx_gpio_banks[] = {
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/* Bank A has 8 IRQs */
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EP93XX_GPIO_BANK("A", 0x00, 0x10, 0, true, false, 64),
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EP93XX_GPIO_BANK("A", 0x00, 0x10, 0x90, 0, true, false, 64),
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/* Bank B has 8 IRQs */
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EP93XX_GPIO_BANK("B", 0x04, 0x14, 8, true, false, 72),
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EP93XX_GPIO_BANK("C", 0x08, 0x18, 40, false, false, 0),
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EP93XX_GPIO_BANK("D", 0x0c, 0x1c, 24, false, false, 0),
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EP93XX_GPIO_BANK("E", 0x20, 0x24, 32, false, false, 0),
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EP93XX_GPIO_BANK("B", 0x04, 0x14, 0xac, 8, true, false, 72),
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EP93XX_GPIO_BANK("C", 0x08, 0x18, 0x00, 40, false, false, 0),
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EP93XX_GPIO_BANK("D", 0x0c, 0x1c, 0x00, 24, false, false, 0),
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EP93XX_GPIO_BANK("E", 0x20, 0x24, 0x00, 32, false, false, 0),
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/* Bank F has 8 IRQs */
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EP93XX_GPIO_BANK("F", 0x30, 0x34, 16, false, true, 0),
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EP93XX_GPIO_BANK("G", 0x38, 0x3c, 48, false, false, 0),
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EP93XX_GPIO_BANK("H", 0x40, 0x44, 56, false, false, 0),
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EP93XX_GPIO_BANK("F", 0x30, 0x34, 0x4c, 16, false, true, 0),
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EP93XX_GPIO_BANK("G", 0x38, 0x3c, 0x00, 48, false, false, 0),
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EP93XX_GPIO_BANK("H", 0x40, 0x44, 0x00, 56, false, false, 0),
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};
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static int ep93xx_gpio_set_config(struct gpio_chip *gc, unsigned offset,
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@ -326,13 +331,14 @@ static int ep93xx_gpio_f_to_irq(struct gpio_chip *gc, unsigned offset)
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return EP93XX_GPIO_F_IRQ_BASE + offset;
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}
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static int ep93xx_gpio_add_bank(struct gpio_chip *gc,
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static int ep93xx_gpio_add_bank(struct ep93xx_gpio_chip *egc,
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struct platform_device *pdev,
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struct ep93xx_gpio *epg,
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struct ep93xx_gpio_bank *bank)
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{
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void __iomem *data = epg->base + bank->data;
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void __iomem *dir = epg->base + bank->dir;
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struct gpio_chip *gc = &egc->gc;
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struct device *dev = &pdev->dev;
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struct gpio_irq_chip *girq;
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int err;
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@ -347,6 +353,12 @@ static int ep93xx_gpio_add_bank(struct gpio_chip *gc,
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girq = &gc->irq;
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if (bank->has_irq || bank->has_hierarchical_irq) {
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gc->set_config = ep93xx_gpio_set_config;
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egc->eic = devm_kcalloc(dev, 1,
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sizeof(*egc->eic),
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GFP_KERNEL);
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if (!egc->eic)
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return -ENOMEM;
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egc->eic->irq_offset = bank->irq;
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girq->chip = &ep93xx_gpio_irq_chip;
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}
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@ -415,7 +427,7 @@ static int ep93xx_gpio_probe(struct platform_device *pdev)
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return PTR_ERR(epg->base);
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for (i = 0; i < ARRAY_SIZE(ep93xx_gpio_banks); i++) {
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struct gpio_chip *gc = &epg->gc[i];
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struct ep93xx_gpio_chip *gc = &epg->gc[i];
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struct ep93xx_gpio_bank *bank = &ep93xx_gpio_banks[i];
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if (ep93xx_gpio_add_bank(gc, pdev, epg, bank))
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