From 8b5f4d0def9caa16527c95e7a4ba47bb8a4d9e1e Mon Sep 17 00:00:00 2001 From: Ben Skeggs Date: Mon, 31 Oct 2011 11:59:07 +1000 Subject: [PATCH] drm/nv50/pm: stabilise transition to 100MHz mclk a bit Signed-off-by: Ben Skeggs --- drivers/gpu/drm/nouveau/nv50_pm.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/drivers/gpu/drm/nouveau/nv50_pm.c b/drivers/gpu/drm/nouveau/nv50_pm.c index 0b82c6075666..961d8f20d27f 100644 --- a/drivers/gpu/drm/nouveau/nv50_pm.c +++ b/drivers/gpu/drm/nouveau/nv50_pm.c @@ -465,7 +465,7 @@ nv50_pm_clocks_pre(struct drm_device *dev, struct nouveau_pm_level *perflvl) /* memory: use pcie refclock if possible, otherwise use mpll */ info->mscript = perflvl->memscript; if (clk_same(perflvl->memory, read_clk(dev, clk_src_href))) { - info->mctrl = nv_rd32(dev, 0x4008) | 0x00000200; + info->mctrl = 0x00000200 | (pll.log2p_bias << 19); info->mcoef = nv_rd32(dev, 0x400c); } else if (perflvl->memory) { @@ -606,7 +606,7 @@ nv50_pm_clocks_set(struct drm_device *dev, void *data) /* modify mpll */ nv_mask(dev, 0x00c040, 0x0000c000, 0x0000c000); - nv_mask(dev, 0x004008, 0x81ff0200, 0x00000200 | info->mctrl); + nv_mask(dev, 0x004008, 0x01ff0200, 0x00000200 | info->mctrl); nv_wr32(dev, 0x00400c, info->mcoef); udelay(100); nv_mask(dev, 0x004008, 0x81ff0200, info->mctrl);