drm/amdgpu: support query vram info for sienna_cichlid
support query vram_module v11 and vram_info v2_5 for sienna_cichlid Signed-off-by: Hawking Zhang <Hawking.Zhang@amd.com> Reviewed-by: Likun Gao <Likun.Gao@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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@ -120,11 +120,13 @@ union umc_info {
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union vram_info {
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struct atom_vram_info_header_v2_3 v23;
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struct atom_vram_info_header_v2_4 v24;
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struct atom_vram_info_header_v2_5 v25;
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};
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union vram_module {
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struct atom_vram_module_v9 v9;
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struct atom_vram_module_v10 v10;
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struct atom_vram_module_v11 v11;
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};
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static int convert_atom_mem_type_to_vram_type(struct amdgpu_device *adev,
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@ -260,6 +262,26 @@ amdgpu_atomfirmware_get_vram_info(struct amdgpu_device *adev,
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if (vram_vendor)
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*vram_vendor = mem_vendor;
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break;
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case 5:
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if (module_id > vram_info->v25.vram_module_num)
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module_id = 0;
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vram_module = (union vram_module *)vram_info->v25.vram_module;
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while (i < module_id) {
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vram_module = (union vram_module *)
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((u8 *)vram_module + vram_module->v11.vram_module_size);
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i++;
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}
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mem_type = vram_module->v11.memory_type;
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if (vram_type)
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*vram_type = convert_atom_mem_type_to_vram_type(adev, mem_type);
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mem_channel_number = vram_module->v11.channel_num;
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mem_channel_width = vram_module->v11.channel_width;
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if (vram_width)
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*vram_width = mem_channel_number * (1 << mem_channel_width);
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mem_vendor = (vram_module->v11.vender_rev_id) & 0xF;
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if (vram_vendor)
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*vram_vendor = mem_vendor;
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break;
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default:
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return -EINVAL;
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}
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