gpio: rcar: Remove obsolete platform data support
Since commit 4baadb9e05 ("ARM: shmobile: r8a7778: remove obsolete
setup code"), Renesas R-Car SoCs are only supported in generic DT-only
ARM multi-platform builds. The driver doesn't need to use platform data
anymore, hence remove platform data configuration.
Make gpio_rcar_priv.has_both_edge_trigger a boolean for consistency with
gpio_rcar_info.has_both_edge_trigger.
Move gpio_rcar_priv.irq_parent down while we're at it, to prevent gaps
on 64-bit.
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Acked-by: Simon Horman <horms+renesas@verge.net.au>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
This commit is contained in:
Geert Uytterhoeven
Linus Walleij
parent
0d1bb2b3b8
commit
8b092be9fd
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@ -25,7 +25,6 @@
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#include <linux/module.h>
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#include <linux/of.h>
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#include <linux/pinctrl/consumer.h>
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#include <linux/platform_data/gpio-rcar.h>
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#include <linux/platform_device.h>
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#include <linux/pm_runtime.h>
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#include <linux/spinlock.h>
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@ -34,12 +33,12 @@
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struct gpio_rcar_priv {
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void __iomem *base;
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spinlock_t lock;
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struct gpio_rcar_config config;
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struct platform_device *pdev;
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struct gpio_chip gpio_chip;
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struct irq_chip irq_chip;
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unsigned int irq_parent;
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struct clk *clk;
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unsigned int irq_parent;
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bool has_both_edge_trigger;
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};
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#define IOINTSEL 0x00 /* General IO/Interrupt Switching Register */
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@ -121,7 +120,7 @@ static void gpio_rcar_config_interrupt_input_mode(struct gpio_rcar_priv *p,
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gpio_rcar_modify_bit(p, EDGLEVEL, hwirq, !level_trigger);
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/* Select one edge or both edges in BOTHEDGE */
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if (p->config.has_both_edge_trigger)
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if (p->has_both_edge_trigger)
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gpio_rcar_modify_bit(p, BOTHEDGE, hwirq, both);
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/* Select "Interrupt Input Mode" in IOINTSEL */
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@ -161,7 +160,7 @@ static int gpio_rcar_irq_set_type(struct irq_data *d, unsigned int type)
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false);
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break;
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case IRQ_TYPE_EDGE_BOTH:
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if (!p->config.has_both_edge_trigger)
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if (!p->has_both_edge_trigger)
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return -EINVAL;
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gpio_rcar_config_interrupt_input_mode(p, hwirq, true, false,
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true);
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@ -355,18 +354,13 @@ static const struct of_device_id gpio_rcar_of_table[] = {
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MODULE_DEVICE_TABLE(of, gpio_rcar_of_table);
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static int gpio_rcar_parse_pdata(struct gpio_rcar_priv *p)
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static int gpio_rcar_parse_dt(struct gpio_rcar_priv *p, unsigned int *npins)
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{
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struct gpio_rcar_config *pdata = dev_get_platdata(&p->pdev->dev);
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struct device_node *np = p->pdev->dev.of_node;
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struct of_phandle_args args;
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int ret;
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if (pdata) {
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p->config = *pdata;
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} else if (IS_ENABLED(CONFIG_OF) && np) {
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const struct of_device_id *match;
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const struct gpio_rcar_info *info;
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struct of_phandle_args args;
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int ret;
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match = of_match_node(gpio_rcar_of_table, np);
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if (!match)
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@ -374,20 +368,15 @@ static int gpio_rcar_parse_pdata(struct gpio_rcar_priv *p)
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info = match->data;
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ret = of_parse_phandle_with_fixed_args(np, "gpio-ranges", 3, 0,
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&args);
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p->config.number_of_pins = ret == 0 ? args.args[2]
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: RCAR_MAX_GPIO_PER_BANK;
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p->config.gpio_base = -1;
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p->config.has_both_edge_trigger = info->has_both_edge_trigger;
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}
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ret = of_parse_phandle_with_fixed_args(np, "gpio-ranges", 3, 0, &args);
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*npins = ret == 0 ? args.args[2] : RCAR_MAX_GPIO_PER_BANK;
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p->has_both_edge_trigger = info->has_both_edge_trigger;
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if (p->config.number_of_pins == 0 ||
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p->config.number_of_pins > RCAR_MAX_GPIO_PER_BANK) {
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if (*npins == 0 || *npins > RCAR_MAX_GPIO_PER_BANK) {
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dev_warn(&p->pdev->dev,
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"Invalid number of gpio lines %u, using %u\n",
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p->config.number_of_pins, RCAR_MAX_GPIO_PER_BANK);
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p->config.number_of_pins = RCAR_MAX_GPIO_PER_BANK;
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"Invalid number of gpio lines %u, using %u\n", *npins,
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RCAR_MAX_GPIO_PER_BANK);
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*npins = RCAR_MAX_GPIO_PER_BANK;
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}
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return 0;
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@ -401,6 +390,7 @@ static int gpio_rcar_probe(struct platform_device *pdev)
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struct irq_chip *irq_chip;
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struct device *dev = &pdev->dev;
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const char *name = dev_name(dev);
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unsigned int npins;
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int ret;
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p = devm_kzalloc(dev, sizeof(*p), GFP_KERNEL);
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@ -410,8 +400,8 @@ static int gpio_rcar_probe(struct platform_device *pdev)
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p->pdev = pdev;
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spin_lock_init(&p->lock);
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/* Get device configuration from DT node or platform data. */
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ret = gpio_rcar_parse_pdata(p);
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/* Get device configuration from DT node */
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ret = gpio_rcar_parse_dt(p, &npins);
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if (ret < 0)
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return ret;
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@ -451,8 +441,8 @@ static int gpio_rcar_probe(struct platform_device *pdev)
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gpio_chip->label = name;
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gpio_chip->parent = dev;
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gpio_chip->owner = THIS_MODULE;
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gpio_chip->base = p->config.gpio_base;
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gpio_chip->ngpio = p->config.number_of_pins;
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gpio_chip->base = -1;
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gpio_chip->ngpio = npins;
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irq_chip = &p->irq_chip;
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irq_chip->name = name;
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@ -468,8 +458,8 @@ static int gpio_rcar_probe(struct platform_device *pdev)
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goto err0;
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}
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ret = gpiochip_irqchip_add(gpio_chip, irq_chip, p->config.irq_base,
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handle_level_irq, IRQ_TYPE_NONE);
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ret = gpiochip_irqchip_add(gpio_chip, irq_chip, 0, handle_level_irq,
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IRQ_TYPE_NONE);
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if (ret) {
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dev_err(dev, "cannot add irqchip\n");
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goto err1;
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@ -483,22 +473,7 @@ static int gpio_rcar_probe(struct platform_device *pdev)
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goto err1;
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}
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dev_info(dev, "driving %d GPIOs\n", p->config.number_of_pins);
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/* warn in case of mismatch if irq base is specified */
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if (p->config.irq_base) {
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ret = irq_find_mapping(gpio_chip->irqdomain, 0);
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if (p->config.irq_base != ret)
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dev_warn(dev, "irq base mismatch (%u/%u)\n",
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p->config.irq_base, ret);
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}
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if (p->config.pctl_name) {
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ret = gpiochip_add_pin_range(gpio_chip, p->config.pctl_name, 0,
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gpio_chip->base, gpio_chip->ngpio);
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if (ret < 0)
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dev_warn(dev, "failed to add pin range\n");
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}
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dev_info(dev, "driving %d GPIOs\n", npins);
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return 0;
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@ -1,29 +0,0 @@
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/*
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* Renesas R-Car GPIO Support
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*
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* Copyright (C) 2013 Magnus Damm
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*/
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#ifndef __GPIO_RCAR_H__
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#define __GPIO_RCAR_H__
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struct gpio_rcar_config {
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int gpio_base;
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unsigned int irq_base;
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unsigned int number_of_pins;
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const char *pctl_name;
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unsigned has_both_edge_trigger:1;
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};
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#define RCAR_GP_PIN(bank, pin) (((bank) * 32) + (pin))
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#endif /* __GPIO_RCAR_H__ */
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