nfp: add more white space to the instruction defines
We need to add longer OP_* defines, move the values away. Purely whitespace commit. Signed-off-by: Jakub Kicinski <jakub.kicinski@netronome.com> Reviewed-by: Simon Horman <simon.horman@netronome.com> Signed-off-by: David S. Miller <davem@davemloft.net>
This commit is contained in:
Jakub Kicinski
David S. Miller
parent
509144e250
commit
8afd9c961e
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@ -53,14 +53,14 @@
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#define UR_REG_IMM_encode(x) (UR_REG_IMM | (x))
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#define UR_REG_IMM_MAX 0x0ffULL
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#define OP_BR_BASE 0x0d800000020ULL
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#define OP_BR_BASE_MASK 0x0f8000c3ce0ULL
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#define OP_BR_MASK 0x0000000001fULL
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#define OP_BR_EV_PIP 0x00000000300ULL
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#define OP_BR_CSS 0x0000003c000ULL
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#define OP_BR_DEFBR 0x00000300000ULL
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#define OP_BR_ADDR_LO 0x007ffc00000ULL
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#define OP_BR_ADDR_HI 0x10000000000ULL
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#define OP_BR_BASE 0x0d800000020ULL
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#define OP_BR_BASE_MASK 0x0f8000c3ce0ULL
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#define OP_BR_MASK 0x0000000001fULL
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#define OP_BR_EV_PIP 0x00000000300ULL
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#define OP_BR_CSS 0x0000003c000ULL
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#define OP_BR_DEFBR 0x00000300000ULL
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#define OP_BR_ADDR_LO 0x007ffc00000ULL
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#define OP_BR_ADDR_HI 0x10000000000ULL
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#define nfp_is_br(_insn) \
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(((_insn) & OP_BR_BASE_MASK) == OP_BR_BASE)
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@ -83,30 +83,30 @@ enum br_ctx_signal_state {
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BR_CSS_NONE = 2,
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};
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#define OP_BBYTE_BASE 0x0c800000000ULL
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#define OP_BB_A_SRC 0x000000000ffULL
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#define OP_BB_BYTE 0x00000000300ULL
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#define OP_BB_B_SRC 0x0000003fc00ULL
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#define OP_BB_I8 0x00000040000ULL
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#define OP_BB_EQ 0x00000080000ULL
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#define OP_BB_DEFBR 0x00000300000ULL
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#define OP_BB_ADDR_LO 0x007ffc00000ULL
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#define OP_BB_ADDR_HI 0x10000000000ULL
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#define OP_BBYTE_BASE 0x0c800000000ULL
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#define OP_BB_A_SRC 0x000000000ffULL
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#define OP_BB_BYTE 0x00000000300ULL
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#define OP_BB_B_SRC 0x0000003fc00ULL
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#define OP_BB_I8 0x00000040000ULL
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#define OP_BB_EQ 0x00000080000ULL
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#define OP_BB_DEFBR 0x00000300000ULL
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#define OP_BB_ADDR_LO 0x007ffc00000ULL
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#define OP_BB_ADDR_HI 0x10000000000ULL
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#define OP_BALU_BASE 0x0e800000000ULL
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#define OP_BA_A_SRC 0x000000003ffULL
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#define OP_BA_B_SRC 0x000000ffc00ULL
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#define OP_BA_DEFBR 0x00000300000ULL
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#define OP_BA_ADDR_HI 0x0007fc00000ULL
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#define OP_BALU_BASE 0x0e800000000ULL
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#define OP_BA_A_SRC 0x000000003ffULL
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#define OP_BA_B_SRC 0x000000ffc00ULL
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#define OP_BA_DEFBR 0x00000300000ULL
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#define OP_BA_ADDR_HI 0x0007fc00000ULL
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#define OP_IMMED_A_SRC 0x000000003ffULL
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#define OP_IMMED_B_SRC 0x000000ffc00ULL
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#define OP_IMMED_IMM 0x0000ff00000ULL
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#define OP_IMMED_WIDTH 0x00060000000ULL
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#define OP_IMMED_INV 0x00080000000ULL
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#define OP_IMMED_SHIFT 0x00600000000ULL
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#define OP_IMMED_BASE 0x0f000000000ULL
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#define OP_IMMED_WR_AB 0x20000000000ULL
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#define OP_IMMED_A_SRC 0x000000003ffULL
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#define OP_IMMED_B_SRC 0x000000ffc00ULL
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#define OP_IMMED_IMM 0x0000ff00000ULL
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#define OP_IMMED_WIDTH 0x00060000000ULL
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#define OP_IMMED_INV 0x00080000000ULL
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#define OP_IMMED_SHIFT 0x00600000000ULL
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#define OP_IMMED_BASE 0x0f000000000ULL
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#define OP_IMMED_WR_AB 0x20000000000ULL
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enum immed_width {
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IMMED_WIDTH_ALL = 0,
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@ -120,17 +120,17 @@ enum immed_shift {
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IMMED_SHIFT_2B = 2,
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};
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#define OP_SHF_BASE 0x08000000000ULL
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#define OP_SHF_A_SRC 0x000000000ffULL
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#define OP_SHF_SC 0x00000000300ULL
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#define OP_SHF_B_SRC 0x0000003fc00ULL
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#define OP_SHF_I8 0x00000040000ULL
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#define OP_SHF_SW 0x00000080000ULL
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#define OP_SHF_DST 0x0000ff00000ULL
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#define OP_SHF_SHIFT 0x001f0000000ULL
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#define OP_SHF_OP 0x00e00000000ULL
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#define OP_SHF_DST_AB 0x01000000000ULL
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#define OP_SHF_WR_AB 0x20000000000ULL
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#define OP_SHF_BASE 0x08000000000ULL
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#define OP_SHF_A_SRC 0x000000000ffULL
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#define OP_SHF_SC 0x00000000300ULL
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#define OP_SHF_B_SRC 0x0000003fc00ULL
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#define OP_SHF_I8 0x00000040000ULL
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#define OP_SHF_SW 0x00000080000ULL
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#define OP_SHF_DST 0x0000ff00000ULL
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#define OP_SHF_SHIFT 0x001f0000000ULL
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#define OP_SHF_OP 0x00e00000000ULL
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#define OP_SHF_DST_AB 0x01000000000ULL
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#define OP_SHF_WR_AB 0x20000000000ULL
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enum shf_op {
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SHF_OP_NONE = 0,
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@ -145,14 +145,14 @@ enum shf_sc {
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SHF_SC_R_DSHF = 3,
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};
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#define OP_ALU_A_SRC 0x000000003ffULL
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#define OP_ALU_B_SRC 0x000000ffc00ULL
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#define OP_ALU_DST 0x0003ff00000ULL
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#define OP_ALU_SW 0x00040000000ULL
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#define OP_ALU_OP 0x00f80000000ULL
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#define OP_ALU_DST_AB 0x01000000000ULL
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#define OP_ALU_BASE 0x0a000000000ULL
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#define OP_ALU_WR_AB 0x20000000000ULL
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#define OP_ALU_A_SRC 0x000000003ffULL
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#define OP_ALU_B_SRC 0x000000ffc00ULL
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#define OP_ALU_DST 0x0003ff00000ULL
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#define OP_ALU_SW 0x00040000000ULL
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#define OP_ALU_OP 0x00f80000000ULL
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#define OP_ALU_DST_AB 0x01000000000ULL
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#define OP_ALU_BASE 0x0a000000000ULL
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#define OP_ALU_WR_AB 0x20000000000ULL
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enum alu_op {
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ALU_OP_NONE = 0x00,
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@ -171,26 +171,26 @@ enum alu_dst_ab {
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ALU_DST_B = 1,
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};
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#define OP_LDF_BASE 0x0c000000000ULL
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#define OP_LDF_A_SRC 0x000000000ffULL
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#define OP_LDF_SC 0x00000000300ULL
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#define OP_LDF_B_SRC 0x0000003fc00ULL
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#define OP_LDF_I8 0x00000040000ULL
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#define OP_LDF_SW 0x00000080000ULL
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#define OP_LDF_ZF 0x00000100000ULL
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#define OP_LDF_BMASK 0x0000f000000ULL
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#define OP_LDF_SHF 0x001f0000000ULL
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#define OP_LDF_WR_AB 0x20000000000ULL
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#define OP_LDF_BASE 0x0c000000000ULL
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#define OP_LDF_A_SRC 0x000000000ffULL
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#define OP_LDF_SC 0x00000000300ULL
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#define OP_LDF_B_SRC 0x0000003fc00ULL
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#define OP_LDF_I8 0x00000040000ULL
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#define OP_LDF_SW 0x00000080000ULL
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#define OP_LDF_ZF 0x00000100000ULL
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#define OP_LDF_BMASK 0x0000f000000ULL
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#define OP_LDF_SHF 0x001f0000000ULL
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#define OP_LDF_WR_AB 0x20000000000ULL
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#define OP_CMD_A_SRC 0x000000000ffULL
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#define OP_CMD_CTX 0x00000000300ULL
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#define OP_CMD_B_SRC 0x0000003fc00ULL
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#define OP_CMD_TOKEN 0x000000c0000ULL
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#define OP_CMD_XFER 0x00001f00000ULL
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#define OP_CMD_CNT 0x0000e000000ULL
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#define OP_CMD_SIG 0x000f0000000ULL
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#define OP_CMD_TGT_CMD 0x07f00000000ULL
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#define OP_CMD_MODE 0x1c0000000000ULL
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#define OP_CMD_A_SRC 0x000000000ffULL
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#define OP_CMD_CTX 0x00000000300ULL
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#define OP_CMD_B_SRC 0x0000003fc00ULL
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#define OP_CMD_TOKEN 0x000000c0000ULL
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#define OP_CMD_XFER 0x00001f00000ULL
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#define OP_CMD_CNT 0x0000e000000ULL
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#define OP_CMD_SIG 0x000f0000000ULL
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#define OP_CMD_TGT_CMD 0x07f00000000ULL
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#define OP_CMD_MODE 0x1c0000000000ULL
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struct cmd_tgt_act {
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u8 token;
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@ -218,11 +218,11 @@ enum cmd_ctx_swap {
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CMD_CTX_NO_SWAP = 3,
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};
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#define OP_LCSR_BASE 0x0fc00000000ULL
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#define OP_LCSR_A_SRC 0x000000003ffULL
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#define OP_LCSR_B_SRC 0x000000ffc00ULL
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#define OP_LCSR_WRITE 0x00000200000ULL
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#define OP_LCSR_ADDR 0x001ffc00000ULL
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#define OP_LCSR_BASE 0x0fc00000000ULL
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#define OP_LCSR_A_SRC 0x000000003ffULL
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#define OP_LCSR_B_SRC 0x000000ffc00ULL
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#define OP_LCSR_WRITE 0x00000200000ULL
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#define OP_LCSR_ADDR 0x001ffc00000ULL
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enum lcsr_wr_src {
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LCSR_WR_AREG,
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@ -230,8 +230,8 @@ enum lcsr_wr_src {
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LCSR_WR_IMM,
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};
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#define OP_CARB_BASE 0x0e000000000ULL
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#define OP_CARB_OR 0x00000010000ULL
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#define OP_CARB_BASE 0x0e000000000ULL
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#define OP_CARB_OR 0x00000010000ULL
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/* Software register representation, independent of operand type */
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#define NN_REG_TYPE GENMASK(31, 24)
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