dt-bindings: power: avs: qcom,cpr: Convert to DT schema
Convert qcom,cpr.txt to DT schema format. Signed-off-by: Yassine Oudjana <y.oudjana@protonmail.com> Reviewed-by: Rob Herring <robh@kernel.org> Signed-off-by: Viresh Kumar <viresh.kumar@linaro.org>
This commit is contained in:
Yassine Oudjana
Viresh Kumar
parent
6b3abe0cfb
commit
8acf5cb92d
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@ -1,130 +0,0 @@
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QCOM CPR (Core Power Reduction)
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CPR (Core Power Reduction) is a technology to reduce core power on a CPU
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or other device. Each OPP of a device corresponds to a "corner" that has
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a range of valid voltages for a particular frequency. While the device is
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running at a particular frequency, CPR monitors dynamic factors such as
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temperature, etc. and suggests adjustments to the voltage to save power
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and meet silicon characteristic requirements.
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- compatible:
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Usage: required
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Value type: <string>
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Definition: should be "qcom,qcs404-cpr", "qcom,cpr" for qcs404
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- reg:
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Usage: required
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Value type: <prop-encoded-array>
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Definition: base address and size of the rbcpr register region
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- interrupts:
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Usage: required
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Value type: <prop-encoded-array>
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Definition: should specify the CPR interrupt
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- clocks:
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Usage: required
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Value type: <prop-encoded-array>
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Definition: phandle to the reference clock
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- clock-names:
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Usage: required
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Value type: <stringlist>
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Definition: must be "ref"
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- vdd-apc-supply:
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Usage: required
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Value type: <phandle>
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Definition: phandle to the vdd-apc-supply regulator
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- #power-domain-cells:
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Usage: required
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Value type: <u32>
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Definition: should be 0
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- operating-points-v2:
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Usage: required
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Value type: <phandle>
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Definition: A phandle to the OPP table containing the
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performance states supported by the CPR
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power domain
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- acc-syscon:
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Usage: optional
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Value type: <phandle>
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Definition: phandle to syscon for writing ACC settings
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- nvmem-cells:
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Usage: required
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Value type: <phandle>
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Definition: phandle to nvmem cells containing the data
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that makes up a fuse corner, for each fuse corner.
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As well as the CPR fuse revision.
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- nvmem-cell-names:
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Usage: required
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Value type: <stringlist>
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Definition: should be "cpr_quotient_offset1", "cpr_quotient_offset2",
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"cpr_quotient_offset3", "cpr_init_voltage1",
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"cpr_init_voltage2", "cpr_init_voltage3", "cpr_quotient1",
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"cpr_quotient2", "cpr_quotient3", "cpr_ring_osc1",
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"cpr_ring_osc2", "cpr_ring_osc3", "cpr_fuse_revision"
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for qcs404.
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Example:
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cpr_opp_table: cpr-opp-table {
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compatible = "operating-points-v2-qcom-level";
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cpr_opp1: opp1 {
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opp-level = <1>;
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qcom,opp-fuse-level = <1>;
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};
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cpr_opp2: opp2 {
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opp-level = <2>;
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qcom,opp-fuse-level = <2>;
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};
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cpr_opp3: opp3 {
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opp-level = <3>;
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qcom,opp-fuse-level = <3>;
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};
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};
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power-controller@b018000 {
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compatible = "qcom,qcs404-cpr", "qcom,cpr";
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reg = <0x0b018000 0x1000>;
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interrupts = <0 15 IRQ_TYPE_EDGE_RISING>;
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clocks = <&xo_board>;
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clock-names = "ref";
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vdd-apc-supply = <&pms405_s3>;
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#power-domain-cells = <0>;
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operating-points-v2 = <&cpr_opp_table>;
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acc-syscon = <&tcsr>;
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nvmem-cells = <&cpr_efuse_quot_offset1>,
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<&cpr_efuse_quot_offset2>,
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<&cpr_efuse_quot_offset3>,
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<&cpr_efuse_init_voltage1>,
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<&cpr_efuse_init_voltage2>,
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<&cpr_efuse_init_voltage3>,
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<&cpr_efuse_quot1>,
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<&cpr_efuse_quot2>,
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<&cpr_efuse_quot3>,
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<&cpr_efuse_ring1>,
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<&cpr_efuse_ring2>,
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<&cpr_efuse_ring3>,
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<&cpr_efuse_revision>;
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nvmem-cell-names = "cpr_quotient_offset1",
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"cpr_quotient_offset2",
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"cpr_quotient_offset3",
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"cpr_init_voltage1",
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"cpr_init_voltage2",
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"cpr_init_voltage3",
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"cpr_quotient1",
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"cpr_quotient2",
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"cpr_quotient3",
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"cpr_ring_osc1",
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"cpr_ring_osc2",
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"cpr_ring_osc3",
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"cpr_fuse_revision";
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};
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@ -0,0 +1,160 @@
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# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
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%YAML 1.2
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---
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$id: http://devicetree.org/schemas/power/avs/qcom,cpr.yaml#
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$schema: http://devicetree.org/meta-schemas/core.yaml#
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title: Qualcomm Core Power Reduction (CPR) bindings
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maintainers:
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- Niklas Cassel <nks@flawful.org>
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description: |
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CPR (Core Power Reduction) is a technology to reduce core power on a CPU
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or other device. Each OPP of a device corresponds to a "corner" that has
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a range of valid voltages for a particular frequency. While the device is
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running at a particular frequency, CPR monitors dynamic factors such as
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temperature, etc. and suggests adjustments to the voltage to save power
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and meet silicon characteristic requirements.
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properties:
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compatible:
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items:
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- enum:
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- qcom,qcs404-cpr
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- const: qcom,cpr
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reg:
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description: Base address and size of the RBCPR register region.
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maxItems: 1
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interrupts:
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maxItems: 1
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clocks:
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items:
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- description: Reference clock.
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clock-names:
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items:
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- const: ref
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vdd-apc-supply:
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description: APC regulator supply.
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'#power-domain-cells':
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const: 0
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operating-points-v2:
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description: |
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A phandle to the OPP table containing the performance states
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supported by the CPR power domain.
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acc-syscon:
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description: A phandle to the syscon used for writing ACC settings.
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nvmem-cells:
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items:
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- description: Corner 1 quotient offset
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- description: Corner 2 quotient offset
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- description: Corner 3 quotient offset
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- description: Corner 1 initial voltage
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- description: Corner 2 initial voltage
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- description: Corner 3 initial voltage
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- description: Corner 1 quotient
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- description: Corner 2 quotient
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- description: Corner 3 quotient
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- description: Corner 1 ring oscillator
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- description: Corner 2 ring oscillator
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- description: Corner 3 ring oscillator
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- description: Fuse revision
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nvmem-cell-names:
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items:
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- const: cpr_quotient_offset1
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- const: cpr_quotient_offset2
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- const: cpr_quotient_offset3
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- const: cpr_init_voltage1
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- const: cpr_init_voltage2
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- const: cpr_init_voltage3
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- const: cpr_quotient1
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- const: cpr_quotient2
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- const: cpr_quotient3
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- const: cpr_ring_osc1
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- const: cpr_ring_osc2
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- const: cpr_ring_osc3
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- const: cpr_fuse_revision
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required:
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- compatible
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- reg
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- interrupts
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- clocks
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- clock-names
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- vdd-apc-supply
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- '#power-domain-cells'
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- operating-points-v2
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- nvmem-cells
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- nvmem-cell-names
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additionalProperties: false
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examples:
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- |
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#include <dt-bindings/interrupt-controller/arm-gic.h>
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cpr_opp_table: opp-table-cpr {
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compatible = "operating-points-v2-qcom-level";
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cpr_opp1: opp1 {
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opp-level = <1>;
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qcom,opp-fuse-level = <1>;
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};
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cpr_opp2: opp2 {
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opp-level = <2>;
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qcom,opp-fuse-level = <2>;
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};
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cpr_opp3: opp3 {
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opp-level = <3>;
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qcom,opp-fuse-level = <3>;
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};
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};
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power-controller@b018000 {
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compatible = "qcom,qcs404-cpr", "qcom,cpr";
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reg = <0x0b018000 0x1000>;
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interrupts = <0 15 IRQ_TYPE_EDGE_RISING>;
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clocks = <&xo_board>;
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clock-names = "ref";
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vdd-apc-supply = <&pms405_s3>;
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#power-domain-cells = <0>;
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operating-points-v2 = <&cpr_opp_table>;
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acc-syscon = <&tcsr>;
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nvmem-cells = <&cpr_efuse_quot_offset1>,
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<&cpr_efuse_quot_offset2>,
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<&cpr_efuse_quot_offset3>,
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<&cpr_efuse_init_voltage1>,
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<&cpr_efuse_init_voltage2>,
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<&cpr_efuse_init_voltage3>,
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<&cpr_efuse_quot1>,
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<&cpr_efuse_quot2>,
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<&cpr_efuse_quot3>,
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<&cpr_efuse_ring1>,
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<&cpr_efuse_ring2>,
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<&cpr_efuse_ring3>,
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<&cpr_efuse_revision>;
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nvmem-cell-names = "cpr_quotient_offset1",
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"cpr_quotient_offset2",
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"cpr_quotient_offset3",
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"cpr_init_voltage1",
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"cpr_init_voltage2",
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"cpr_init_voltage3",
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"cpr_quotient1",
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"cpr_quotient2",
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"cpr_quotient3",
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"cpr_ring_osc1",
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"cpr_ring_osc2",
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"cpr_ring_osc3",
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"cpr_fuse_revision";
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};
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@ -15933,7 +15933,7 @@ M: Niklas Cassel <nks@flawful.org>
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L: linux-pm@vger.kernel.org
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L: linux-arm-msm@vger.kernel.org
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S: Maintained
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F: Documentation/devicetree/bindings/power/avs/qcom,cpr.txt
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F: Documentation/devicetree/bindings/power/avs/qcom,cpr.yaml
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F: drivers/soc/qcom/cpr.c
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QUALCOMM CPUFREQ DRIVER MSM8996/APQ8096
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