pwm: sprd: Add Spreadtrum PWM support
This patch adds the Spreadtrum PWM support, which provides maximum 4 channels. Signed-off-by: Neo Hou <neo.hou@unisoc.com> Signed-off-by: Baolin Wang <baolin.wang@linaro.org> Signed-off-by: Thierry Reding <thierry.reding@gmail.com>
This commit is contained in:
Baolin Wang
Thierry Reding
parent
bdaadd5948
commit
8aae4b02e8
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@ -423,6 +423,17 @@ config PWM_SPEAR
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To compile this driver as a module, choose M here: the module
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will be called pwm-spear.
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config PWM_SPRD
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tristate "Spreadtrum PWM support"
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depends on ARCH_SPRD || COMPILE_TEST
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depends on HAS_IOMEM
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help
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Generic PWM framework driver for the PWM controller on
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Spreadtrum SoCs.
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To compile this driver as a module, choose M here: the module
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will be called pwm-sprd.
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config PWM_STI
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tristate "STiH4xx PWM support"
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depends on ARCH_STI
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@ -41,6 +41,7 @@ obj-$(CONFIG_PWM_ROCKCHIP) += pwm-rockchip.o
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obj-$(CONFIG_PWM_SAMSUNG) += pwm-samsung.o
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obj-$(CONFIG_PWM_SIFIVE) += pwm-sifive.o
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obj-$(CONFIG_PWM_SPEAR) += pwm-spear.o
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obj-$(CONFIG_PWM_SPRD) += pwm-sprd.o
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obj-$(CONFIG_PWM_STI) += pwm-sti.o
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obj-$(CONFIG_PWM_STM32) += pwm-stm32.o
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obj-$(CONFIG_PWM_STM32_LP) += pwm-stm32-lp.o
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@ -0,0 +1,309 @@
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// SPDX-License-Identifier: GPL-2.0
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/*
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* Copyright (C) 2019 Spreadtrum Communications Inc.
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*/
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#include <linux/clk.h>
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#include <linux/err.h>
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#include <linux/io.h>
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#include <linux/math64.h>
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#include <linux/module.h>
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#include <linux/platform_device.h>
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#include <linux/pwm.h>
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#define SPRD_PWM_PRESCALE 0x0
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#define SPRD_PWM_MOD 0x4
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#define SPRD_PWM_DUTY 0x8
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#define SPRD_PWM_ENABLE 0x18
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#define SPRD_PWM_MOD_MAX GENMASK(7, 0)
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#define SPRD_PWM_DUTY_MSK GENMASK(15, 0)
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#define SPRD_PWM_PRESCALE_MSK GENMASK(7, 0)
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#define SPRD_PWM_ENABLE_BIT BIT(0)
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#define SPRD_PWM_CHN_NUM 4
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#define SPRD_PWM_REGS_SHIFT 5
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#define SPRD_PWM_CHN_CLKS_NUM 2
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#define SPRD_PWM_CHN_OUTPUT_CLK 1
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struct sprd_pwm_chn {
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struct clk_bulk_data clks[SPRD_PWM_CHN_CLKS_NUM];
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u32 clk_rate;
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};
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struct sprd_pwm_chip {
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void __iomem *base;
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struct device *dev;
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struct pwm_chip chip;
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int num_pwms;
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struct sprd_pwm_chn chn[SPRD_PWM_CHN_NUM];
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};
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/*
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* The list of clocks required by PWM channels, and each channel has 2 clocks:
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* enable clock and pwm clock.
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*/
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static const char * const sprd_pwm_clks[] = {
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"enable0", "pwm0",
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"enable1", "pwm1",
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"enable2", "pwm2",
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"enable3", "pwm3",
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};
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static u32 sprd_pwm_read(struct sprd_pwm_chip *spc, u32 hwid, u32 reg)
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{
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u32 offset = reg + (hwid << SPRD_PWM_REGS_SHIFT);
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return readl_relaxed(spc->base + offset);
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}
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static void sprd_pwm_write(struct sprd_pwm_chip *spc, u32 hwid,
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u32 reg, u32 val)
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{
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u32 offset = reg + (hwid << SPRD_PWM_REGS_SHIFT);
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writel_relaxed(val, spc->base + offset);
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}
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static void sprd_pwm_get_state(struct pwm_chip *chip, struct pwm_device *pwm,
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struct pwm_state *state)
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{
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struct sprd_pwm_chip *spc =
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container_of(chip, struct sprd_pwm_chip, chip);
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struct sprd_pwm_chn *chn = &spc->chn[pwm->hwpwm];
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u32 val, duty, prescale;
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u64 tmp;
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int ret;
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/*
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* The clocks to PWM channel has to be enabled first before
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* reading to the registers.
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*/
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ret = clk_bulk_prepare_enable(SPRD_PWM_CHN_CLKS_NUM, chn->clks);
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if (ret) {
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dev_err(spc->dev, "failed to enable pwm%u clocks\n",
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pwm->hwpwm);
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return;
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}
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val = sprd_pwm_read(spc, pwm->hwpwm, SPRD_PWM_ENABLE);
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if (val & SPRD_PWM_ENABLE_BIT)
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state->enabled = true;
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else
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state->enabled = false;
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/*
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* The hardware provides a counter that is feed by the source clock.
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* The period length is (PRESCALE + 1) * MOD counter steps.
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* The duty cycle length is (PRESCALE + 1) * DUTY counter steps.
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* Thus the period_ns and duty_ns calculation formula should be:
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* period_ns = NSEC_PER_SEC * (prescale + 1) * mod / clk_rate
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* duty_ns = NSEC_PER_SEC * (prescale + 1) * duty / clk_rate
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*/
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val = sprd_pwm_read(spc, pwm->hwpwm, SPRD_PWM_PRESCALE);
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prescale = val & SPRD_PWM_PRESCALE_MSK;
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tmp = (prescale + 1) * NSEC_PER_SEC * SPRD_PWM_MOD_MAX;
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state->period = DIV_ROUND_CLOSEST_ULL(tmp, chn->clk_rate);
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val = sprd_pwm_read(spc, pwm->hwpwm, SPRD_PWM_DUTY);
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duty = val & SPRD_PWM_DUTY_MSK;
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tmp = (prescale + 1) * NSEC_PER_SEC * duty;
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state->duty_cycle = DIV_ROUND_CLOSEST_ULL(tmp, chn->clk_rate);
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/* Disable PWM clocks if the PWM channel is not in enable state. */
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if (!state->enabled)
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clk_bulk_disable_unprepare(SPRD_PWM_CHN_CLKS_NUM, chn->clks);
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}
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static int sprd_pwm_config(struct sprd_pwm_chip *spc, struct pwm_device *pwm,
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int duty_ns, int period_ns)
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{
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struct sprd_pwm_chn *chn = &spc->chn[pwm->hwpwm];
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u32 prescale, duty;
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u64 tmp;
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/*
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* The hardware provides a counter that is feed by the source clock.
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* The period length is (PRESCALE + 1) * MOD counter steps.
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* The duty cycle length is (PRESCALE + 1) * DUTY counter steps.
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*
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* To keep the maths simple we're always using MOD = SPRD_PWM_MOD_MAX.
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* The value for PRESCALE is selected such that the resulting period
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* gets the maximal length not bigger than the requested one with the
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* given settings (MOD = SPRD_PWM_MOD_MAX and input clock).
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*/
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duty = duty_ns * SPRD_PWM_MOD_MAX / period_ns;
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tmp = (u64)chn->clk_rate * period_ns;
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do_div(tmp, NSEC_PER_SEC);
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prescale = DIV_ROUND_CLOSEST_ULL(tmp, SPRD_PWM_MOD_MAX) - 1;
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if (prescale > SPRD_PWM_PRESCALE_MSK)
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prescale = SPRD_PWM_PRESCALE_MSK;
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/*
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* Note: Writing DUTY triggers the hardware to actually apply the
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* values written to MOD and DUTY to the output, so must keep writing
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* DUTY last.
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*
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* The hardware can ensures that current running period is completed
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* before changing a new configuration to avoid mixed settings.
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*/
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sprd_pwm_write(spc, pwm->hwpwm, SPRD_PWM_PRESCALE, prescale);
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sprd_pwm_write(spc, pwm->hwpwm, SPRD_PWM_MOD, SPRD_PWM_MOD_MAX);
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sprd_pwm_write(spc, pwm->hwpwm, SPRD_PWM_DUTY, duty);
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return 0;
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}
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static int sprd_pwm_apply(struct pwm_chip *chip, struct pwm_device *pwm,
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struct pwm_state *state)
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{
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struct sprd_pwm_chip *spc =
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container_of(chip, struct sprd_pwm_chip, chip);
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struct sprd_pwm_chn *chn = &spc->chn[pwm->hwpwm];
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struct pwm_state *cstate = &pwm->state;
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int ret;
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if (state->enabled) {
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if (!cstate->enabled) {
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/*
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* The clocks to PWM channel has to be enabled first
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* before writing to the registers.
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*/
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ret = clk_bulk_prepare_enable(SPRD_PWM_CHN_CLKS_NUM,
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chn->clks);
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if (ret) {
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dev_err(spc->dev,
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"failed to enable pwm%u clocks\n",
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pwm->hwpwm);
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return ret;
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}
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}
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if (state->period != cstate->period ||
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state->duty_cycle != cstate->duty_cycle) {
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ret = sprd_pwm_config(spc, pwm, state->duty_cycle,
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state->period);
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if (ret)
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return ret;
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}
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sprd_pwm_write(spc, pwm->hwpwm, SPRD_PWM_ENABLE, 1);
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} else if (cstate->enabled) {
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/*
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* Note: After setting SPRD_PWM_ENABLE to zero, the controller
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* will not wait for current period to be completed, instead it
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* will stop the PWM channel immediately.
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*/
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sprd_pwm_write(spc, pwm->hwpwm, SPRD_PWM_ENABLE, 0);
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clk_bulk_disable_unprepare(SPRD_PWM_CHN_CLKS_NUM, chn->clks);
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}
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return 0;
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}
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static const struct pwm_ops sprd_pwm_ops = {
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.apply = sprd_pwm_apply,
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.get_state = sprd_pwm_get_state,
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.owner = THIS_MODULE,
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};
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static int sprd_pwm_clk_init(struct sprd_pwm_chip *spc)
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{
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struct clk *clk_pwm;
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int ret, i;
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for (i = 0; i < SPRD_PWM_CHN_NUM; i++) {
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struct sprd_pwm_chn *chn = &spc->chn[i];
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int j;
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for (j = 0; j < SPRD_PWM_CHN_CLKS_NUM; ++j)
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chn->clks[j].id =
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sprd_pwm_clks[i * SPRD_PWM_CHN_CLKS_NUM + j];
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ret = devm_clk_bulk_get(spc->dev, SPRD_PWM_CHN_CLKS_NUM,
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chn->clks);
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if (ret) {
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if (ret == -ENOENT)
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break;
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if (ret != -EPROBE_DEFER)
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dev_err(spc->dev,
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"failed to get channel clocks\n");
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return ret;
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}
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clk_pwm = chn->clks[SPRD_PWM_CHN_OUTPUT_CLK].clk;
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chn->clk_rate = clk_get_rate(clk_pwm);
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}
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if (!i) {
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dev_err(spc->dev, "no available PWM channels\n");
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return -ENODEV;
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}
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spc->num_pwms = i;
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return 0;
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}
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static int sprd_pwm_probe(struct platform_device *pdev)
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{
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struct sprd_pwm_chip *spc;
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int ret;
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spc = devm_kzalloc(&pdev->dev, sizeof(*spc), GFP_KERNEL);
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if (!spc)
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return -ENOMEM;
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spc->base = devm_platform_ioremap_resource(pdev, 0);
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if (IS_ERR(spc->base))
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return PTR_ERR(spc->base);
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spc->dev = &pdev->dev;
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platform_set_drvdata(pdev, spc);
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ret = sprd_pwm_clk_init(spc);
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if (ret)
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return ret;
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spc->chip.dev = &pdev->dev;
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spc->chip.ops = &sprd_pwm_ops;
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spc->chip.base = -1;
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spc->chip.npwm = spc->num_pwms;
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ret = pwmchip_add(&spc->chip);
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if (ret)
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dev_err(&pdev->dev, "failed to add PWM chip\n");
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return ret;
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}
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static int sprd_pwm_remove(struct platform_device *pdev)
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{
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struct sprd_pwm_chip *spc = platform_get_drvdata(pdev);
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return pwmchip_remove(&spc->chip);
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}
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static const struct of_device_id sprd_pwm_of_match[] = {
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{ .compatible = "sprd,ums512-pwm", },
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{ },
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};
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MODULE_DEVICE_TABLE(of, sprd_pwm_of_match);
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static struct platform_driver sprd_pwm_driver = {
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.driver = {
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.name = "sprd-pwm",
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.of_match_table = sprd_pwm_of_match,
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},
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.probe = sprd_pwm_probe,
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.remove = sprd_pwm_remove,
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};
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module_platform_driver(sprd_pwm_driver);
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MODULE_DESCRIPTION("Spreadtrum PWM Driver");
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MODULE_LICENSE("GPL v2");
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