DVB (2421): Fixed oddities at firmware download
- Fixed oddities at firmware download - more tolerant vs crystal frequency offset - lower sampling clock Signed-off-by: Hartmut Hackmann <hartmut.hackmann@t-online.de> Signed-off-by: Mauro Carvalho Chehab <mchehab@brturbo.com.br>
This commit is contained in:
Hartmut Hackmann
Mauro Carvalho Chehab
parent
d3707add61
commit
8a8e9c281d
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@ -271,32 +271,57 @@ static int tda10045h_set_bandwidth(struct tda1004x_state *state,
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static int tda10046h_set_bandwidth(struct tda1004x_state *state,
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fe_bandwidth_t bandwidth)
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{
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static u8 bandwidth_6mhz[] = { 0x80, 0x15, 0xfe, 0xab, 0x8e };
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static u8 bandwidth_7mhz[] = { 0x6e, 0x02, 0x53, 0xc8, 0x25 };
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static u8 bandwidth_8mhz[] = { 0x60, 0x12, 0xa8, 0xe4, 0xbd };
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static u8 bandwidth_6mhz_53M[] = { 0x7b, 0x2e, 0x11, 0xf0, 0xd2 };
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static u8 bandwidth_7mhz_53M[] = { 0x6a, 0x02, 0x6a, 0x43, 0x9f };
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static u8 bandwidth_8mhz_53M[] = { 0x5c, 0x32, 0xc2, 0x96, 0x6d };
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static u8 bandwidth_6mhz_48M[] = { 0x70, 0x02, 0x49, 0x24, 0x92 };
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static u8 bandwidth_7mhz_48M[] = { 0x60, 0x02, 0xaa, 0xaa, 0xab };
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static u8 bandwidth_8mhz_48M[] = { 0x54, 0x03, 0x0c, 0x30, 0xc3 };
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int tda10046_clk53m;
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if ((state->config->if_freq == TDA10046_FREQ_045) ||
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(state->config->if_freq == TDA10046_FREQ_052))
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tda10046_clk53m = 0;
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else
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tda10046_clk53m = 1;
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switch (bandwidth) {
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case BANDWIDTH_6_MHZ:
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tda1004x_write_buf(state, TDA10046H_TIME_WREF1, bandwidth_6mhz, sizeof(bandwidth_6mhz));
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if (tda10046_clk53m)
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tda1004x_write_buf(state, TDA10046H_TIME_WREF1, bandwidth_6mhz_53M,
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sizeof(bandwidth_6mhz_53M));
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else
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tda1004x_write_buf(state, TDA10046H_TIME_WREF1, bandwidth_6mhz_48M,
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sizeof(bandwidth_6mhz_48M));
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if (state->config->if_freq == TDA10046_FREQ_045) {
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tda1004x_write_byteI(state, TDA10046H_FREQ_PHY2_MSB, 0x09);
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tda1004x_write_byteI(state, TDA10046H_FREQ_PHY2_LSB, 0x4f);
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tda1004x_write_byteI(state, TDA10046H_FREQ_PHY2_MSB, 0x0a);
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tda1004x_write_byteI(state, TDA10046H_FREQ_PHY2_LSB, 0xab);
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}
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break;
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case BANDWIDTH_7_MHZ:
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tda1004x_write_buf(state, TDA10046H_TIME_WREF1, bandwidth_7mhz, sizeof(bandwidth_7mhz));
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if (tda10046_clk53m)
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tda1004x_write_buf(state, TDA10046H_TIME_WREF1, bandwidth_7mhz_53M,
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sizeof(bandwidth_7mhz_53M));
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else
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tda1004x_write_buf(state, TDA10046H_TIME_WREF1, bandwidth_7mhz_48M,
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sizeof(bandwidth_7mhz_48M));
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if (state->config->if_freq == TDA10046_FREQ_045) {
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tda1004x_write_byteI(state, TDA10046H_FREQ_PHY2_MSB, 0x0a);
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tda1004x_write_byteI(state, TDA10046H_FREQ_PHY2_LSB, 0x79);
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tda1004x_write_byteI(state, TDA10046H_FREQ_PHY2_MSB, 0x0c);
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tda1004x_write_byteI(state, TDA10046H_FREQ_PHY2_LSB, 0x00);
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}
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break;
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case BANDWIDTH_8_MHZ:
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tda1004x_write_buf(state, TDA10046H_TIME_WREF1, bandwidth_8mhz, sizeof(bandwidth_8mhz));
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if (tda10046_clk53m)
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tda1004x_write_buf(state, TDA10046H_TIME_WREF1, bandwidth_8mhz_53M,
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sizeof(bandwidth_8mhz_53M));
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else
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tda1004x_write_buf(state, TDA10046H_TIME_WREF1, bandwidth_8mhz_48M,
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sizeof(bandwidth_8mhz_48M));
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if (state->config->if_freq == TDA10046_FREQ_045) {
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tda1004x_write_byteI(state, TDA10046H_FREQ_PHY2_MSB, 0x0b);
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tda1004x_write_byteI(state, TDA10046H_FREQ_PHY2_LSB, 0xa3);
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tda1004x_write_byteI(state, TDA10046H_FREQ_PHY2_MSB, 0x0d);
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tda1004x_write_byteI(state, TDA10046H_FREQ_PHY2_LSB, 0x55);
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}
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break;
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@ -418,9 +443,22 @@ static int tda10045_fwupload(struct dvb_frontend* fe)
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static void tda10046_init_plls(struct dvb_frontend* fe)
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{
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struct tda1004x_state* state = fe->demodulator_priv;
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int tda10046_clk53m;
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if ((state->config->if_freq == TDA10046_FREQ_045) ||
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(state->config->if_freq == TDA10046_FREQ_052))
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tda10046_clk53m = 0;
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else
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tda10046_clk53m = 1;
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tda1004x_write_byteI(state, TDA10046H_CONFPLL1, 0xf0);
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tda1004x_write_byteI(state, TDA10046H_CONFPLL2, 0x0a); // PLL M = 10
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if(tda10046_clk53m) {
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printk(KERN_INFO "tda1004x: setting up plls for 53MHz sampling clock\n");
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tda1004x_write_byteI(state, TDA10046H_CONFPLL2, 0x08); // PLL M = 8
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} else {
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printk(KERN_INFO "tda1004x: setting up plls for 48MHz sampling clock\n");
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tda1004x_write_byteI(state, TDA10046H_CONFPLL2, 0x03); // PLL M = 3
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}
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if (state->config->xtal_freq == TDA10046_XTAL_4M ) {
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dprintk("%s: setting up PLLs for a 4 MHz Xtal\n", __FUNCTION__);
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tda1004x_write_byteI(state, TDA10046H_CONFPLL3, 0); // PLL P = N = 0
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@ -428,26 +466,32 @@ static void tda10046_init_plls(struct dvb_frontend* fe)
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dprintk("%s: setting up PLLs for a 16 MHz Xtal\n", __FUNCTION__);
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tda1004x_write_byteI(state, TDA10046H_CONFPLL3, 3); // PLL P = 0, N = 3
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}
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tda1004x_write_byteI(state, TDA10046H_FREQ_OFFSET, 99);
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if(tda10046_clk53m)
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tda1004x_write_byteI(state, TDA10046H_FREQ_OFFSET, 0x67);
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else
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tda1004x_write_byteI(state, TDA10046H_FREQ_OFFSET, 0x72);
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/* Note clock frequency is handled implicitly */
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switch (state->config->if_freq) {
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case TDA10046_FREQ_3617:
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tda1004x_write_byteI(state, TDA10046H_FREQ_PHY2_MSB, 0xd4);
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tda1004x_write_byteI(state, TDA10046H_FREQ_PHY2_LSB, 0x2c);
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break;
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case TDA10046_FREQ_3613:
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tda1004x_write_byteI(state, TDA10046H_FREQ_PHY2_MSB, 0xd4);
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tda1004x_write_byteI(state, TDA10046H_FREQ_PHY2_LSB, 0x13);
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break;
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case TDA10046_FREQ_045:
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tda1004x_write_byteI(state, TDA10046H_FREQ_PHY2_MSB, 0x0b);
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tda1004x_write_byteI(state, TDA10046H_FREQ_PHY2_LSB, 0xa3);
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tda1004x_write_byteI(state, TDA10046H_FREQ_PHY2_MSB, 0x0c);
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tda1004x_write_byteI(state, TDA10046H_FREQ_PHY2_LSB, 0x00);
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break;
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case TDA10046_FREQ_052:
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tda1004x_write_byteI(state, TDA10046H_FREQ_PHY2_MSB, 0x0c);
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tda1004x_write_byteI(state, TDA10046H_FREQ_PHY2_LSB, 0x06);
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tda1004x_write_byteI(state, TDA10046H_FREQ_PHY2_MSB, 0x0d);
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tda1004x_write_byteI(state, TDA10046H_FREQ_PHY2_LSB, 0xc7);
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break;
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case TDA10046_FREQ_3617:
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tda1004x_write_byteI(state, TDA10046H_FREQ_PHY2_MSB, 0xd7);
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tda1004x_write_byteI(state, TDA10046H_FREQ_PHY2_LSB, 0x59);
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break;
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case TDA10046_FREQ_3613:
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tda1004x_write_byteI(state, TDA10046H_FREQ_PHY2_MSB, 0xd7);
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tda1004x_write_byteI(state, TDA10046H_FREQ_PHY2_LSB, 0x3f);
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break;
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}
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tda10046h_set_bandwidth(state, BANDWIDTH_8_MHZ); // default bandwidth 8 MHz
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/* let the PLLs settle */
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msleep(120);
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}
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static int tda10046_fwupload(struct dvb_frontend* fe)
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@ -462,13 +506,13 @@ static int tda10046_fwupload(struct dvb_frontend* fe)
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/* let the clocks recover from sleep */
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msleep(5);
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/* The PLLs need to be reprogrammed after sleep */
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tda10046_init_plls(fe);
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/* don't re-upload unless necessary */
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if (tda1004x_check_upload_ok(state) == 0)
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return 0;
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/* set parameters */
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tda10046_init_plls(fe);
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if (state->config->request_firmware != NULL) {
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/* request the firmware, this will block until someone uploads it */
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printk(KERN_INFO "tda1004x: waiting for firmware upload...\n");
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@ -484,7 +528,6 @@ static int tda10046_fwupload(struct dvb_frontend* fe)
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return ret;
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} else {
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/* boot from firmware eeprom */
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/* Hac Note: we might need to do some GPIO Magic here */
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printk(KERN_INFO "tda1004x: booting from eeprom\n");
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tda1004x_write_mask(state, TDA1004X_CONFC4, 4, 4);
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msleep(300);
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@ -606,10 +649,9 @@ static int tda10046_init(struct dvb_frontend* fe)
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// tda setup
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tda1004x_write_mask(state, TDA1004X_CONFC4, 0x20, 0); // disable DSP watchdog timer
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tda1004x_write_byteI(state, TDA1004X_AUTO, 7); // select HP stream
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tda1004x_write_byteI(state, TDA1004X_CONFC1, 8); // disable pulse killer
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tda1004x_write_byteI(state, TDA1004X_AUTO, 0x87); // 100 ppm crystal, select HP stream
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tda1004x_write_byteI(state, TDA1004X_CONFC1, 8); // disable pulse killer
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tda10046_init_plls(fe);
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switch (state->config->agc_config) {
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case TDA10046_AGC_DEFAULT:
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tda1004x_write_byteI(state, TDA10046H_AGC_CONF, 0x00); // AGC setup
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@ -626,25 +668,22 @@ static int tda10046_init(struct dvb_frontend* fe)
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case TDA10046_AGC_TDA827X:
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tda1004x_write_byteI(state, TDA10046H_AGC_CONF, 0x02); // AGC setup
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tda1004x_write_byteI(state, TDA10046H_AGC_THR, 0x70); // AGC Threshold
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tda1004x_write_byteI(state, TDA10046H_AGC_RENORM, 0x0E); // Gain Renormalize
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tda1004x_write_byteI(state, TDA10046H_CONF_POLARITY, 0x60); // set AGC polarities
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tda1004x_write_byteI(state, TDA10046H_AGC_RENORM, 0x08); // Gain Renormalize
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tda1004x_write_byteI(state, TDA10046H_CONF_POLARITY, 0x6a); // set AGC polarities
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break;
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}
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tda1004x_write_byteI(state, TDA1004X_CONFADC2, 0x38);
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tda1004x_write_byteI(state, TDA10046H_CONF_TRISTATE1, 0x61); // Turn both AGC outputs on
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tda1004x_write_byteI(state, TDA10046H_AGC_TUN_MIN, 0); // }
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tda1004x_write_byteI(state, TDA10046H_AGC_TUN_MAX, 0xff); // } AGC min/max values
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tda1004x_write_byteI(state, TDA10046H_AGC_IF_MIN, 0); // }
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tda1004x_write_byteI(state, TDA10046H_AGC_IF_MAX, 0xff); // }
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tda1004x_write_byteI(state, TDA10046H_AGC_GAINS, 1); // IF gain 2, TUN gain 1
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tda1004x_write_byteI(state, TDA10046H_AGC_GAINS, 0x12); // IF gain 2, TUN gain 1
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tda1004x_write_byteI(state, TDA10046H_CVBER_CTRL, 0x1a); // 10^6 VBER measurement bits
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tda1004x_write_byteI(state, TDA1004X_CONF_TS1, 7); // MPEG2 interface config
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tda1004x_write_byteI(state, TDA1004X_CONF_TS2, 0xc0); // MPEG2 interface config
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tda1004x_write_mask(state, 0x3a, 0x80, state->config->invert_oclk << 7);
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tda1004x_write_byteI(state, TDA10046H_CONF_TRISTATE2, 0xe1); // tristate setup
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tda1004x_write_byteI(state, TDA10046H_GPIO_OUT_SEL, 0xcc); // GPIO output config
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tda1004x_write_byteI(state, TDA10046H_GPIO_SELECT, 8); // GPIO select
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state->initialised = 1;
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return 0;
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}
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@ -686,9 +725,9 @@ static int tda1004x_set_fe(struct dvb_frontend* fe,
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// Set standard params.. or put them to auto
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if ((fe_params->u.ofdm.code_rate_HP == FEC_AUTO) ||
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(fe_params->u.ofdm.code_rate_LP == FEC_AUTO) ||
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(fe_params->u.ofdm.constellation == QAM_AUTO) ||
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(fe_params->u.ofdm.hierarchy_information == HIERARCHY_AUTO)) {
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(fe_params->u.ofdm.code_rate_LP == FEC_AUTO) ||
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(fe_params->u.ofdm.constellation == QAM_AUTO) ||
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(fe_params->u.ofdm.hierarchy_information == HIERARCHY_AUTO)) {
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tda1004x_write_mask(state, TDA1004X_AUTO, 1, 1); // enable auto
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tda1004x_write_mask(state, TDA1004X_IN_CONF1, 0x03, 0); // turn off constellation bits
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tda1004x_write_mask(state, TDA1004X_IN_CONF1, 0x60, 0); // turn off hierarchy bits
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@ -851,6 +890,7 @@ static int tda1004x_set_fe(struct dvb_frontend* fe,
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static int tda1004x_get_fe(struct dvb_frontend* fe, struct dvb_frontend_parameters *fe_params)
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{
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struct tda1004x_state* state = fe->demodulator_priv;
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dprintk("%s\n", __FUNCTION__);
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// inversion status
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@ -875,16 +915,18 @@ static int tda1004x_get_fe(struct dvb_frontend* fe, struct dvb_frontend_paramete
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break;
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}
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break;
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case TDA1004X_DEMOD_TDA10046:
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switch (tda1004x_read_byte(state, TDA10046H_TIME_WREF1)) {
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case 0x60:
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case 0x5c:
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case 0x54:
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fe_params->u.ofdm.bandwidth = BANDWIDTH_8_MHZ;
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break;
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case 0x6e:
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case 0x6a:
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case 0x60:
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fe_params->u.ofdm.bandwidth = BANDWIDTH_7_MHZ;
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break;
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case 0x80:
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case 0x7b:
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case 0x70:
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fe_params->u.ofdm.bandwidth = BANDWIDTH_6_MHZ;
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break;
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}
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