crypto: ux500 - Add driver for HASH hardware
This adds a driver for the ST-Ericsson ux500 hash hardware module. The driver implements support for SHA-1 and SHA-2. Acked-by: Linus Walleij <linus.walleij@linaro.org> Signed-off-by: Andreas Westin <andreas.westin@stericsson.com> Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au>
This commit is contained in:
Andreas Westin
Herbert Xu
parent
2789c08fff
commit
8a63b1994c
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@ -8,6 +8,11 @@
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#include <linux/dmaengine.h>
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#include <plat/ste_dma40.h>
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struct hash_platform_data {
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void *mem_to_engine;
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bool (*dma_filter)(struct dma_chan *chan, void *filter_param);
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};
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struct cryp_platform_data {
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struct stedma40_chan_cfg mem_to_engine;
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struct stedma40_chan_cfg engine_to_mem;
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@ -12,6 +12,15 @@ config CRYPTO_DEV_UX500_CRYP
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This selects the crypto driver for the UX500_CRYP hardware. It supports
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AES-ECB, CBC and CTR with keys sizes of 128, 192 and 256 bit sizes.
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config CRYPTO_DEV_UX500_HASH
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tristate "UX500 crypto driver for HASH block"
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depends on CRYPTO_DEV_UX500
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select CRYPTO_HASH
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select CRYPTO_HMAC
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help
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This selects the hash driver for the UX500_HASH hardware.
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Depends on UX500/STM DMA if running in DMA mode.
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config CRYPTO_DEV_UX500_DEBUG
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bool "Activate ux500 platform debug-mode for crypto and hash block"
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depends on CRYPTO_DEV_UX500_CRYP || CRYPTO_DEV_UX500_HASH
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@ -4,4 +4,5 @@
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# License terms: GNU General Public License (GPL) version 2
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#
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obj-$(CONFIG_CRYPTO_DEV_UX500_HASH) += hash/
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obj-$(CONFIG_CRYPTO_DEV_UX500_CRYP) += cryp/
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@ -0,0 +1,11 @@
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#
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# Copyright (C) ST-Ericsson SA 2010
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# Author: Shujuan Chen (shujuan.chen@stericsson.com)
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# License terms: GNU General Public License (GPL) version 2
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#
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ifdef CONFIG_CRYPTO_DEV_UX500_DEBUG
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CFLAGS_hash_core.o := -DDEBUG -O0
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endif
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obj-$(CONFIG_CRYPTO_DEV_UX500_HASH) += ux500_hash.o
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ux500_hash-objs := hash_core.o
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@ -0,0 +1,395 @@
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/*
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* Copyright (C) ST-Ericsson SA 2010
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* Author: Shujuan Chen (shujuan.chen@stericsson.com)
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* Author: Joakim Bech (joakim.xx.bech@stericsson.com)
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* Author: Berne Hebark (berne.hebark@stericsson.com))
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* License terms: GNU General Public License (GPL) version 2
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*/
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#ifndef _HASH_ALG_H
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#define _HASH_ALG_H
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#include <linux/bitops.h>
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#define HASH_BLOCK_SIZE 64
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#define HASH_DMA_ALIGN_SIZE 4
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#define HASH_DMA_PERFORMANCE_MIN_SIZE 1024
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#define HASH_BYTES_PER_WORD 4
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/* Maximum value of the length's high word */
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#define HASH_HIGH_WORD_MAX_VAL 0xFFFFFFFFUL
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/* Power on Reset values HASH registers */
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#define HASH_RESET_CR_VALUE 0x0
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#define HASH_RESET_STR_VALUE 0x0
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/* Number of context swap registers */
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#define HASH_CSR_COUNT 52
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#define HASH_RESET_CSRX_REG_VALUE 0x0
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#define HASH_RESET_CSFULL_REG_VALUE 0x0
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#define HASH_RESET_CSDATAIN_REG_VALUE 0x0
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#define HASH_RESET_INDEX_VAL 0x0
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#define HASH_RESET_BIT_INDEX_VAL 0x0
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#define HASH_RESET_BUFFER_VAL 0x0
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#define HASH_RESET_LEN_HIGH_VAL 0x0
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#define HASH_RESET_LEN_LOW_VAL 0x0
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/* Control register bitfields */
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#define HASH_CR_RESUME_MASK 0x11FCF
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#define HASH_CR_SWITCHON_POS 31
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#define HASH_CR_SWITCHON_MASK BIT(31)
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#define HASH_CR_EMPTYMSG_POS 20
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#define HASH_CR_EMPTYMSG_MASK BIT(20)
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#define HASH_CR_DINF_POS 12
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#define HASH_CR_DINF_MASK BIT(12)
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#define HASH_CR_NBW_POS 8
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#define HASH_CR_NBW_MASK 0x00000F00UL
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#define HASH_CR_LKEY_POS 16
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#define HASH_CR_LKEY_MASK BIT(16)
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#define HASH_CR_ALGO_POS 7
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#define HASH_CR_ALGO_MASK BIT(7)
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#define HASH_CR_MODE_POS 6
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#define HASH_CR_MODE_MASK BIT(6)
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#define HASH_CR_DATAFORM_POS 4
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#define HASH_CR_DATAFORM_MASK (BIT(4) | BIT(5))
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#define HASH_CR_DMAE_POS 3
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#define HASH_CR_DMAE_MASK BIT(3)
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#define HASH_CR_INIT_POS 2
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#define HASH_CR_INIT_MASK BIT(2)
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#define HASH_CR_PRIVN_POS 1
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#define HASH_CR_PRIVN_MASK BIT(1)
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#define HASH_CR_SECN_POS 0
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#define HASH_CR_SECN_MASK BIT(0)
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/* Start register bitfields */
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#define HASH_STR_DCAL_POS 8
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#define HASH_STR_DCAL_MASK BIT(8)
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#define HASH_STR_DEFAULT 0x0
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#define HASH_STR_NBLW_POS 0
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#define HASH_STR_NBLW_MASK 0x0000001FUL
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#define HASH_NBLW_MAX_VAL 0x1F
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/* PrimeCell IDs */
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#define HASH_P_ID0 0xE0
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#define HASH_P_ID1 0x05
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#define HASH_P_ID2 0x38
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#define HASH_P_ID3 0x00
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#define HASH_CELL_ID0 0x0D
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#define HASH_CELL_ID1 0xF0
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#define HASH_CELL_ID2 0x05
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#define HASH_CELL_ID3 0xB1
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#define HASH_SET_BITS(reg_name, mask) \
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writel_relaxed((readl_relaxed(reg_name) | mask), reg_name)
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#define HASH_CLEAR_BITS(reg_name, mask) \
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writel_relaxed((readl_relaxed(reg_name) & ~mask), reg_name)
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#define HASH_PUT_BITS(reg, val, shift, mask) \
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writel_relaxed(((readl(reg) & ~(mask)) | \
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(((u32)val << shift) & (mask))), reg)
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#define HASH_SET_DIN(val, len) writesl(&device_data->base->din, (val), (len))
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#define HASH_INITIALIZE \
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HASH_PUT_BITS( \
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&device_data->base->cr, \
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0x01, HASH_CR_INIT_POS, \
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HASH_CR_INIT_MASK)
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#define HASH_SET_DATA_FORMAT(data_format) \
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HASH_PUT_BITS( \
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&device_data->base->cr, \
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(u32) (data_format), HASH_CR_DATAFORM_POS, \
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HASH_CR_DATAFORM_MASK)
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#define HASH_SET_NBLW(val) \
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HASH_PUT_BITS( \
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&device_data->base->str, \
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(u32) (val), HASH_STR_NBLW_POS, \
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HASH_STR_NBLW_MASK)
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#define HASH_SET_DCAL \
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HASH_PUT_BITS( \
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&device_data->base->str, \
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0x01, HASH_STR_DCAL_POS, \
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HASH_STR_DCAL_MASK)
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/* Hardware access method */
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enum hash_mode {
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HASH_MODE_CPU,
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HASH_MODE_DMA
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};
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/**
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* struct uint64 - Structure to handle 64 bits integers.
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* @high_word: Most significant bits.
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* @low_word: Least significant bits.
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*
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* Used to handle 64 bits integers.
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*/
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struct uint64 {
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u32 high_word;
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u32 low_word;
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};
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/**
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* struct hash_register - Contains all registers in ux500 hash hardware.
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* @cr: HASH control register (0x000).
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* @din: HASH data input register (0x004).
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* @str: HASH start register (0x008).
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* @hx: HASH digest register 0..7 (0x00c-0x01C).
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* @padding0: Reserved (0x02C).
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* @itcr: Integration test control register (0x080).
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* @itip: Integration test input register (0x084).
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* @itop: Integration test output register (0x088).
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* @padding1: Reserved (0x08C).
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* @csfull: HASH context full register (0x0F8).
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* @csdatain: HASH context swap data input register (0x0FC).
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* @csrx: HASH context swap register 0..51 (0x100-0x1CC).
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* @padding2: Reserved (0x1D0).
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* @periphid0: HASH peripheral identification register 0 (0xFE0).
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* @periphid1: HASH peripheral identification register 1 (0xFE4).
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* @periphid2: HASH peripheral identification register 2 (0xFE8).
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* @periphid3: HASH peripheral identification register 3 (0xFEC).
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* @cellid0: HASH PCell identification register 0 (0xFF0).
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* @cellid1: HASH PCell identification register 1 (0xFF4).
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* @cellid2: HASH PCell identification register 2 (0xFF8).
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* @cellid3: HASH PCell identification register 3 (0xFFC).
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*
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* The device communicates to the HASH via 32-bit-wide control registers
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* accessible via the 32-bit width AMBA rev. 2.0 AHB Bus. Below is a structure
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* with the registers used.
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*/
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struct hash_register {
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u32 cr;
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u32 din;
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u32 str;
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u32 hx[8];
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u32 padding0[(0x080 - 0x02C) / sizeof(u32)];
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u32 itcr;
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u32 itip;
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u32 itop;
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u32 padding1[(0x0F8 - 0x08C) / sizeof(u32)];
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u32 csfull;
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u32 csdatain;
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u32 csrx[HASH_CSR_COUNT];
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u32 padding2[(0xFE0 - 0x1D0) / sizeof(u32)];
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u32 periphid0;
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u32 periphid1;
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u32 periphid2;
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u32 periphid3;
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u32 cellid0;
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u32 cellid1;
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u32 cellid2;
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u32 cellid3;
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};
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/**
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* struct hash_state - Hash context state.
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* @temp_cr: Temporary HASH Control Register.
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* @str_reg: HASH Start Register.
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* @din_reg: HASH Data Input Register.
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* @csr[52]: HASH Context Swap Registers 0-39.
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* @csfull: HASH Context Swap Registers 40 ie Status flags.
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* @csdatain: HASH Context Swap Registers 41 ie Input data.
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* @buffer: Working buffer for messages going to the hardware.
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* @length: Length of the part of message hashed so far (floor(N/64) * 64).
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* @index: Valid number of bytes in buffer (N % 64).
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* @bit_index: Valid number of bits in buffer (N % 8).
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*
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* This structure is used between context switches, i.e. when ongoing jobs are
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* interupted with new jobs. When this happens we need to store intermediate
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* results in software.
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*
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* WARNING: "index" is the member of the structure, to be sure that "buffer"
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* is aligned on a 4-bytes boundary. This is highly implementation dependent
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* and MUST be checked whenever this code is ported on new platforms.
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*/
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struct hash_state {
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u32 temp_cr;
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u32 str_reg;
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u32 din_reg;
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u32 csr[52];
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u32 csfull;
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u32 csdatain;
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u32 buffer[HASH_BLOCK_SIZE / sizeof(u32)];
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struct uint64 length;
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u8 index;
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u8 bit_index;
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};
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/**
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* enum hash_device_id - HASH device ID.
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* @HASH_DEVICE_ID_0: Hash hardware with ID 0
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* @HASH_DEVICE_ID_1: Hash hardware with ID 1
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*/
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enum hash_device_id {
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HASH_DEVICE_ID_0 = 0,
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HASH_DEVICE_ID_1 = 1
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};
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/**
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* enum hash_data_format - HASH data format.
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* @HASH_DATA_32_BITS: 32 bits data format
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* @HASH_DATA_16_BITS: 16 bits data format
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* @HASH_DATA_8_BITS: 8 bits data format.
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* @HASH_DATA_1_BITS: 1 bit data format.
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*/
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enum hash_data_format {
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HASH_DATA_32_BITS = 0x0,
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HASH_DATA_16_BITS = 0x1,
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HASH_DATA_8_BITS = 0x2,
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HASH_DATA_1_BIT = 0x3
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};
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/**
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* enum hash_algo - Enumeration for selecting between SHA1 or SHA2 algorithm.
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* @HASH_ALGO_SHA1: Indicates that SHA1 is used.
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* @HASH_ALGO_SHA2: Indicates that SHA2 (SHA256) is used.
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*/
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enum hash_algo {
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HASH_ALGO_SHA1 = 0x0,
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HASH_ALGO_SHA256 = 0x1
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};
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/**
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* enum hash_op - Enumeration for selecting between HASH or HMAC mode.
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* @HASH_OPER_MODE_HASH: Indicates usage of normal HASH mode.
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* @HASH_OPER_MODE_HMAC: Indicates usage of HMAC.
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*/
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enum hash_op {
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HASH_OPER_MODE_HASH = 0x0,
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HASH_OPER_MODE_HMAC = 0x1
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};
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/**
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* struct hash_config - Configuration data for the hardware.
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* @data_format: Format of data entered into the hash data in register.
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* @algorithm: Algorithm selection bit.
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* @oper_mode: Operating mode selection bit.
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*/
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struct hash_config {
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int data_format;
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int algorithm;
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int oper_mode;
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};
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/**
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* struct hash_dma - Structure used for dma.
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* @mask: DMA capabilities bitmap mask.
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* @complete: Used to maintain state for a "completion".
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* @chan_mem2hash: DMA channel.
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* @cfg_mem2hash: DMA channel configuration.
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* @sg_len: Scatterlist length.
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* @sg: Scatterlist.
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* @nents: Number of sg entries.
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*/
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struct hash_dma {
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dma_cap_mask_t mask;
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struct completion complete;
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struct dma_chan *chan_mem2hash;
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void *cfg_mem2hash;
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int sg_len;
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struct scatterlist *sg;
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int nents;
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};
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/**
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* struct hash_ctx - The context used for hash calculations.
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* @key: The key used in the operation.
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* @keylen: The length of the key.
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* @state: The state of the current calculations.
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* @config: The current configuration.
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* @digestsize: The size of current digest.
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* @device: Pointer to the device structure.
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*/
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struct hash_ctx {
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u8 *key;
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u32 keylen;
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struct hash_config config;
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int digestsize;
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struct hash_device_data *device;
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};
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/**
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* struct hash_ctx - The request context used for hash calculations.
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* @state: The state of the current calculations.
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* @dma_mode: Used in special cases (workaround), e.g. need to change to
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* cpu mode, if not supported/working in dma mode.
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* @updated: Indicates if hardware is initialized for new operations.
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*/
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struct hash_req_ctx {
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struct hash_state state;
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bool dma_mode;
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u8 updated;
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};
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/**
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* struct hash_device_data - structure for a hash device.
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* @base: Pointer to the hardware base address.
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* @list_node: For inclusion in klist.
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* @dev: Pointer to the device dev structure.
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* @ctx_lock: Spinlock for current_ctx.
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* @current_ctx: Pointer to the currently allocated context.
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* @power_state: TRUE = power state on, FALSE = power state off.
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* @power_state_lock: Spinlock for power_state.
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* @regulator: Pointer to the device's power control.
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* @clk: Pointer to the device's clock control.
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* @restore_dev_state: TRUE = saved state, FALSE = no saved state.
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* @dma: Structure used for dma.
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*/
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struct hash_device_data {
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struct hash_register __iomem *base;
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struct klist_node list_node;
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struct device *dev;
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struct spinlock ctx_lock;
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struct hash_ctx *current_ctx;
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bool power_state;
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struct spinlock power_state_lock;
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struct regulator *regulator;
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struct clk *clk;
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bool restore_dev_state;
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struct hash_state state; /* Used for saving and resuming state */
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struct hash_dma dma;
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};
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int hash_check_hw(struct hash_device_data *device_data);
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int hash_setconfiguration(struct hash_device_data *device_data,
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struct hash_config *config);
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void hash_begin(struct hash_device_data *device_data, struct hash_ctx *ctx);
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void hash_get_digest(struct hash_device_data *device_data,
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u8 *digest, int algorithm);
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int hash_hw_update(struct ahash_request *req);
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int hash_save_state(struct hash_device_data *device_data,
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struct hash_state *state);
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int hash_resume_state(struct hash_device_data *device_data,
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const struct hash_state *state);
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#endif
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