Merge branch 'qed-coalesce'
Sudarsana Reddy Kalluru says: ==================== qed*: coalesce parameters config support. The patch series adds the support for config/read of the adapter coalesce parameters. Patch (1) adds the qed infrastructure/APIs for the support and patch (2) adds the driver support for following ethtool commands: ethtool -c|--show-coalesce ethX ethtool -C|--coalesce ethX [rx-usecs N] [tx-usecs N] ==================== Signed-off-by: David S. Miller <davem@davemloft.net>
This commit is contained in:
commit
8a0b0751ff
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@ -2222,6 +2222,110 @@ int qed_fw_rss_eng(struct qed_hwfn *p_hwfn,
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return 0;
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}
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static int qed_set_coalesce(struct qed_hwfn *p_hwfn, struct qed_ptt *p_ptt,
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u32 hw_addr, void *p_eth_qzone,
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size_t eth_qzone_size, u8 timeset)
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{
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struct coalescing_timeset *p_coal_timeset;
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if (p_hwfn->cdev->int_coalescing_mode != QED_COAL_MODE_ENABLE) {
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DP_NOTICE(p_hwfn, "Coalescing configuration not enabled\n");
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return -EINVAL;
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}
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p_coal_timeset = p_eth_qzone;
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memset(p_coal_timeset, 0, eth_qzone_size);
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SET_FIELD(p_coal_timeset->value, COALESCING_TIMESET_TIMESET, timeset);
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SET_FIELD(p_coal_timeset->value, COALESCING_TIMESET_VALID, 1);
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qed_memcpy_to(p_hwfn, p_ptt, hw_addr, p_eth_qzone, eth_qzone_size);
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return 0;
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}
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int qed_set_rxq_coalesce(struct qed_hwfn *p_hwfn, struct qed_ptt *p_ptt,
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u16 coalesce, u8 qid, u16 sb_id)
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{
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struct ustorm_eth_queue_zone eth_qzone;
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u8 timeset, timer_res;
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u16 fw_qid = 0;
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u32 address;
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int rc;
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/* Coalesce = (timeset << timer-resolution), timeset is 7bit wide */
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if (coalesce <= 0x7F) {
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timer_res = 0;
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} else if (coalesce <= 0xFF) {
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timer_res = 1;
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} else if (coalesce <= 0x1FF) {
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timer_res = 2;
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} else {
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DP_ERR(p_hwfn, "Invalid coalesce value - %d\n", coalesce);
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return -EINVAL;
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}
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timeset = (u8)(coalesce >> timer_res);
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rc = qed_fw_l2_queue(p_hwfn, (u16)qid, &fw_qid);
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if (rc)
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return rc;
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rc = qed_int_set_timer_res(p_hwfn, p_ptt, timer_res, sb_id, false);
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if (rc)
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goto out;
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address = BAR0_MAP_REG_USDM_RAM + USTORM_ETH_QUEUE_ZONE_OFFSET(fw_qid);
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rc = qed_set_coalesce(p_hwfn, p_ptt, address, ð_qzone,
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sizeof(struct ustorm_eth_queue_zone), timeset);
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if (rc)
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goto out;
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p_hwfn->cdev->rx_coalesce_usecs = coalesce;
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out:
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return rc;
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}
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int qed_set_txq_coalesce(struct qed_hwfn *p_hwfn, struct qed_ptt *p_ptt,
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u16 coalesce, u8 qid, u16 sb_id)
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{
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struct xstorm_eth_queue_zone eth_qzone;
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u8 timeset, timer_res;
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u16 fw_qid = 0;
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u32 address;
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int rc;
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/* Coalesce = (timeset << timer-resolution), timeset is 7bit wide */
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if (coalesce <= 0x7F) {
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timer_res = 0;
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} else if (coalesce <= 0xFF) {
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timer_res = 1;
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} else if (coalesce <= 0x1FF) {
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timer_res = 2;
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} else {
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DP_ERR(p_hwfn, "Invalid coalesce value - %d\n", coalesce);
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return -EINVAL;
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}
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timeset = (u8)(coalesce >> timer_res);
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rc = qed_fw_l2_queue(p_hwfn, (u16)qid, &fw_qid);
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if (rc)
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return rc;
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rc = qed_int_set_timer_res(p_hwfn, p_ptt, timer_res, sb_id, true);
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if (rc)
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goto out;
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address = BAR0_MAP_REG_XSDM_RAM + XSTORM_ETH_QUEUE_ZONE_OFFSET(fw_qid);
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rc = qed_set_coalesce(p_hwfn, p_ptt, address, ð_qzone,
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sizeof(struct xstorm_eth_queue_zone), timeset);
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if (rc)
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goto out;
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p_hwfn->cdev->tx_coalesce_usecs = coalesce;
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out:
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return rc;
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}
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/* Calculate final WFQ values for all vports and configure them.
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* After this configuration each vport will have
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* approx min rate = min_pf_rate * (vport_wfq / QED_WFQ_UNIT)
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@ -212,6 +212,20 @@ qed_dmae_host2grc(struct qed_hwfn *p_hwfn,
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u32 size_in_dwords,
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u32 flags);
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/**
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* @brief qed_dmae_grc2host - Read data from dmae data offset
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* to source address using the given ptt
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*
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* @param p_ptt
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* @param grc_addr (dmae_data_offset)
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* @param dest_addr
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* @param size_in_dwords
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* @param flags - one of the flags defined above
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*/
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int qed_dmae_grc2host(struct qed_hwfn *p_hwfn, struct qed_ptt *p_ptt,
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u32 grc_addr, dma_addr_t dest_addr, u32 size_in_dwords,
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u32 flags);
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/**
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* @brief qed_dmae_host2host - copy data from to source address
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* to a destination adress (for SRIOV) using the given ptt
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@ -308,4 +322,37 @@ int qed_fw_rss_eng(struct qed_hwfn *p_hwfn,
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int qed_final_cleanup(struct qed_hwfn *p_hwfn,
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struct qed_ptt *p_ptt, u16 id, bool is_vf);
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/**
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* @brief qed_set_rxq_coalesce - Configure coalesce parameters for an Rx queue
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* The fact that we can configure coalescing to up to 511, but on varying
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* accuracy [the bigger the value the less accurate] up to a mistake of 3usec
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* for the highest values.
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*
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* @param p_hwfn
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* @param p_ptt
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* @param coalesce - Coalesce value in micro seconds.
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* @param qid - Queue index.
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* @param qid - SB Id
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*
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* @return int
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*/
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int qed_set_rxq_coalesce(struct qed_hwfn *p_hwfn, struct qed_ptt *p_ptt,
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u16 coalesce, u8 qid, u16 sb_id);
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/**
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* @brief qed_set_txq_coalesce - Configure coalesce parameters for a Tx queue
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* While the API allows setting coalescing per-qid, all tx queues sharing a
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* SB should be in same range [i.e., either 0-0x7f, 0x80-0xff or 0x100-0x1ff]
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* otherwise configuration would break.
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*
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* @param p_hwfn
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* @param p_ptt
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* @param coalesce - Coalesce value in micro seconds.
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* @param qid - Queue index.
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* @param qid - SB Id
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*
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* @return int
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*/
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int qed_set_txq_coalesce(struct qed_hwfn *p_hwfn, struct qed_ptt *p_ptt,
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u16 coalesce, u8 qid, u16 sb_id);
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#endif
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@ -768,6 +768,29 @@ int qed_dmae_host2grc(struct qed_hwfn *p_hwfn,
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return rc;
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}
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int
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qed_dmae_grc2host(struct qed_hwfn *p_hwfn, struct qed_ptt *p_ptt, u32 grc_addr,
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dma_addr_t dest_addr, u32 size_in_dwords, u32 flags)
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{
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u32 grc_addr_in_dw = grc_addr / sizeof(u32);
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struct qed_dmae_params params;
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int rc;
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memset(¶ms, 0, sizeof(struct qed_dmae_params));
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params.flags = flags;
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mutex_lock(&p_hwfn->dmae_info.mutex);
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rc = qed_dmae_execute_command(p_hwfn, p_ptt, grc_addr_in_dw,
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dest_addr, QED_DMAE_ADDRESS_GRC,
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QED_DMAE_ADDRESS_HOST_VIRT,
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size_in_dwords, ¶ms);
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mutex_unlock(&p_hwfn->dmae_info.mutex);
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return rc;
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}
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int
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qed_dmae_host2host(struct qed_hwfn *p_hwfn,
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struct qed_ptt *p_ptt,
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@ -2418,6 +2418,7 @@ void qed_init_cau_sb_entry(struct qed_hwfn *p_hwfn,
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{
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struct qed_dev *cdev = p_hwfn->cdev;
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u32 cau_state;
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u8 timer_res;
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memset(p_sb_entry, 0, sizeof(*p_sb_entry));
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@ -2443,6 +2444,23 @@ void qed_init_cau_sb_entry(struct qed_hwfn *p_hwfn,
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cdev->tx_coalesce_usecs = QED_CAU_DEF_TX_USECS;
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}
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/* Coalesce = (timeset << timer-res), timeset is 7bit wide */
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if (cdev->rx_coalesce_usecs <= 0x7F)
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timer_res = 0;
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else if (cdev->rx_coalesce_usecs <= 0xFF)
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timer_res = 1;
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else
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timer_res = 2;
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SET_FIELD(p_sb_entry->params, CAU_SB_ENTRY_TIMER_RES0, timer_res);
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if (cdev->tx_coalesce_usecs <= 0x7F)
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timer_res = 0;
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else if (cdev->tx_coalesce_usecs <= 0xFF)
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timer_res = 1;
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else
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timer_res = 2;
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SET_FIELD(p_sb_entry->params, CAU_SB_ENTRY_TIMER_RES1, timer_res);
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SET_FIELD(p_sb_entry->data, CAU_SB_ENTRY_STATE0, cau_state);
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SET_FIELD(p_sb_entry->data, CAU_SB_ENTRY_STATE1, cau_state);
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}
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@ -2484,17 +2502,28 @@ void qed_int_cau_conf_sb(struct qed_hwfn *p_hwfn,
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/* Configure pi coalescing if set */
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if (p_hwfn->cdev->int_coalescing_mode == QED_COAL_MODE_ENABLE) {
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u8 timeset = p_hwfn->cdev->rx_coalesce_usecs >>
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(QED_CAU_DEF_RX_TIMER_RES + 1);
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u8 timeset, timer_res;
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u8 num_tc = 1, i;
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/* timeset = (coalesce >> timer-res), timeset is 7bit wide */
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if (p_hwfn->cdev->rx_coalesce_usecs <= 0x7F)
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timer_res = 0;
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else if (p_hwfn->cdev->rx_coalesce_usecs <= 0xFF)
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timer_res = 1;
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else
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timer_res = 2;
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timeset = (u8)(p_hwfn->cdev->rx_coalesce_usecs >> timer_res);
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qed_int_cau_conf_pi(p_hwfn, p_ptt, igu_sb_id, RX_PI,
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QED_COAL_RX_STATE_MACHINE,
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timeset);
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timeset = p_hwfn->cdev->tx_coalesce_usecs >>
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(QED_CAU_DEF_TX_TIMER_RES + 1);
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if (p_hwfn->cdev->tx_coalesce_usecs <= 0x7F)
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timer_res = 0;
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else if (p_hwfn->cdev->tx_coalesce_usecs <= 0xFF)
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timer_res = 1;
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else
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timer_res = 2;
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timeset = (u8)(p_hwfn->cdev->tx_coalesce_usecs >> timer_res);
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for (i = 0; i < num_tc; i++) {
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qed_int_cau_conf_pi(p_hwfn, p_ptt,
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igu_sb_id, TX_PI(i),
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@ -3199,3 +3228,39 @@ void qed_int_disable_post_isr_release(struct qed_dev *cdev)
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for_each_hwfn(cdev, i)
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cdev->hwfns[i].b_int_requested = false;
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}
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int qed_int_set_timer_res(struct qed_hwfn *p_hwfn, struct qed_ptt *p_ptt,
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u8 timer_res, u16 sb_id, bool tx)
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{
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struct cau_sb_entry sb_entry;
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int rc;
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if (!p_hwfn->hw_init_done) {
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DP_ERR(p_hwfn, "hardware not initialized yet\n");
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return -EINVAL;
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}
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rc = qed_dmae_grc2host(p_hwfn, p_ptt, CAU_REG_SB_VAR_MEMORY +
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sb_id * sizeof(u64),
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(u64)(uintptr_t)&sb_entry, 2, 0);
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if (rc) {
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DP_ERR(p_hwfn, "dmae_grc2host failed %d\n", rc);
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return rc;
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}
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if (tx)
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SET_FIELD(sb_entry.params, CAU_SB_ENTRY_TIMER_RES1, timer_res);
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else
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SET_FIELD(sb_entry.params, CAU_SB_ENTRY_TIMER_RES0, timer_res);
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rc = qed_dmae_host2grc(p_hwfn, p_ptt,
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(u64)(uintptr_t)&sb_entry,
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CAU_REG_SB_VAR_MEMORY +
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sb_id * sizeof(u64), 2, 0);
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if (rc) {
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DP_ERR(p_hwfn, "dmae_host2grc failed %d\n", rc);
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return rc;
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}
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return rc;
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}
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|
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@ -389,6 +389,9 @@ void qed_init_cau_sb_entry(struct qed_hwfn *p_hwfn,
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u16 vf_number,
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u8 vf_valid);
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int qed_int_set_timer_res(struct qed_hwfn *p_hwfn, struct qed_ptt *p_ptt,
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u8 timer_res, u16 sb_id, bool tx);
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#define QED_MAPPING_MEMORY_SIZE(dev) (NUM_OF_SBS(dev))
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#endif
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|
|
|
@ -1303,6 +1303,38 @@ static int qed_drain(struct qed_dev *cdev)
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return 0;
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}
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static void qed_get_coalesce(struct qed_dev *cdev, u16 *rx_coal, u16 *tx_coal)
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{
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*rx_coal = cdev->rx_coalesce_usecs;
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*tx_coal = cdev->tx_coalesce_usecs;
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}
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static int qed_set_coalesce(struct qed_dev *cdev, u16 rx_coal, u16 tx_coal,
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u8 qid, u16 sb_id)
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{
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struct qed_hwfn *hwfn;
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struct qed_ptt *ptt;
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int hwfn_index;
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int status = 0;
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hwfn_index = qid % cdev->num_hwfns;
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hwfn = &cdev->hwfns[hwfn_index];
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ptt = qed_ptt_acquire(hwfn);
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if (!ptt)
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return -EAGAIN;
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status = qed_set_rxq_coalesce(hwfn, ptt, rx_coal,
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qid / cdev->num_hwfns, sb_id);
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if (status)
|
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goto out;
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status = qed_set_txq_coalesce(hwfn, ptt, tx_coal,
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qid / cdev->num_hwfns, sb_id);
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out:
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qed_ptt_release(hwfn, ptt);
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return status;
|
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}
|
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|
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static int qed_set_led(struct qed_dev *cdev, enum qed_led_mode mode)
|
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{
|
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struct qed_hwfn *hwfn = QED_LEADING_HWFN(cdev);
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|
@ -1349,5 +1381,7 @@ const struct qed_common_ops qed_common_ops_pass = {
|
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.update_msglvl = &qed_init_dp,
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.chain_alloc = &qed_chain_alloc,
|
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.chain_free = &qed_chain_free,
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.get_coalesce = &qed_get_coalesce,
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.set_coalesce = &qed_set_coalesce,
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.set_led = &qed_set_led,
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};
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|
|
|
@ -80,6 +80,8 @@
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0x1f00000UL
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#define BAR0_MAP_REG_TSDM_RAM \
|
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0x1c80000UL
|
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#define BAR0_MAP_REG_XSDM_RAM \
|
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0x1e00000UL
|
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#define NIG_REG_RX_LLH_BRB_GATE_DNTFWD_PERPF \
|
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0x5011f4UL
|
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#define PRS_REG_SEARCH_TCP \
|
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|
|
|
@ -426,6 +426,57 @@ static u32 qede_get_link(struct net_device *dev)
|
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return current_link.link_up;
|
||||
}
|
||||
|
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static int qede_get_coalesce(struct net_device *dev,
|
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struct ethtool_coalesce *coal)
|
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{
|
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struct qede_dev *edev = netdev_priv(dev);
|
||||
|
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memset(coal, 0, sizeof(struct ethtool_coalesce));
|
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edev->ops->common->get_coalesce(edev->cdev,
|
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(u16 *)&coal->rx_coalesce_usecs,
|
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(u16 *)&coal->tx_coalesce_usecs);
|
||||
|
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return 0;
|
||||
}
|
||||
|
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static int qede_set_coalesce(struct net_device *dev,
|
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struct ethtool_coalesce *coal)
|
||||
{
|
||||
struct qede_dev *edev = netdev_priv(dev);
|
||||
int i, rc = 0;
|
||||
u16 rxc, txc;
|
||||
u8 sb_id;
|
||||
|
||||
if (!netif_running(dev)) {
|
||||
DP_INFO(edev, "Interface is down\n");
|
||||
return -EINVAL;
|
||||
}
|
||||
|
||||
if (coal->rx_coalesce_usecs > QED_COALESCE_MAX ||
|
||||
coal->tx_coalesce_usecs > QED_COALESCE_MAX) {
|
||||
DP_INFO(edev,
|
||||
"Can't support requested %s coalesce value [max supported value %d]\n",
|
||||
coal->rx_coalesce_usecs > QED_COALESCE_MAX ? "rx"
|
||||
: "tx",
|
||||
QED_COALESCE_MAX);
|
||||
return -EINVAL;
|
||||
}
|
||||
|
||||
rxc = (u16)coal->rx_coalesce_usecs;
|
||||
txc = (u16)coal->tx_coalesce_usecs;
|
||||
for_each_rss(i) {
|
||||
sb_id = edev->fp_array[i].sb_info->igu_sb_id;
|
||||
rc = edev->ops->common->set_coalesce(edev->cdev, rxc, txc,
|
||||
(u8)i, sb_id);
|
||||
if (rc) {
|
||||
DP_INFO(edev, "Set coalesce error, rc = %d\n", rc);
|
||||
return rc;
|
||||
}
|
||||
}
|
||||
|
||||
return rc;
|
||||
}
|
||||
|
||||
static void qede_get_ringparam(struct net_device *dev,
|
||||
struct ethtool_ringparam *ering)
|
||||
{
|
||||
|
@ -1139,6 +1190,8 @@ static const struct ethtool_ops qede_ethtool_ops = {
|
|||
.set_msglevel = qede_set_msglevel,
|
||||
.nway_reset = qede_nway_reset,
|
||||
.get_link = qede_get_link,
|
||||
.get_coalesce = qede_get_coalesce,
|
||||
.set_coalesce = qede_set_coalesce,
|
||||
.get_ringparam = qede_get_ringparam,
|
||||
.set_ringparam = qede_set_ringparam,
|
||||
.get_pauseparam = qede_get_pauseparam,
|
||||
|
|
|
@ -488,6 +488,30 @@ struct qed_common_ops {
|
|||
void (*chain_free)(struct qed_dev *cdev,
|
||||
struct qed_chain *p_chain);
|
||||
|
||||
/**
|
||||
* @brief get_coalesce - Get coalesce parameters in usec
|
||||
*
|
||||
* @param cdev
|
||||
* @param rx_coal - Rx coalesce value in usec
|
||||
* @param tx_coal - Tx coalesce value in usec
|
||||
*
|
||||
*/
|
||||
void (*get_coalesce)(struct qed_dev *cdev, u16 *rx_coal, u16 *tx_coal);
|
||||
|
||||
/**
|
||||
* @brief set_coalesce - Configure Rx coalesce value in usec
|
||||
*
|
||||
* @param cdev
|
||||
* @param rx_coal - Rx coalesce value in usec
|
||||
* @param tx_coal - Tx coalesce value in usec
|
||||
* @param qid - Queue index
|
||||
* @param sb_id - Status Block Id
|
||||
*
|
||||
* @return 0 on success, error otherwise.
|
||||
*/
|
||||
int (*set_coalesce)(struct qed_dev *cdev, u16 rx_coal, u16 tx_coal,
|
||||
u8 qid, u16 sb_id);
|
||||
|
||||
/**
|
||||
* @brief set_led - Configure LED mode
|
||||
*
|
||||
|
|
Loading…
Reference in New Issue