From 1dd5581354547641ef6e19e6a90727a985b1be87 Mon Sep 17 00:00:00 2001 From: David Lechner Date: Fri, 6 Jan 2017 11:07:01 -0800 Subject: [PATCH 01/14] ARM: dts: keystone: Add "ti,da830-uart" compatible string The TI Keystone SoCs have extra UART registers beyond the standard 8250 registers, so we need a new compatible string to indicate this. Also, at least one of these registers uses the full 32 bits, so we need to specify reg-io-width in addition to reg-shift. "ns16550a" is left in the compatible specification since it does work as long as the bootloader configures the SoC UART power management registers. Signed-off-by: David Lechner Signed-off-by: Santosh Shilimkar --- arch/arm/boot/dts/keystone-k2g.dtsi | 2 +- arch/arm/boot/dts/keystone-k2l.dtsi | 4 ++-- arch/arm/boot/dts/keystone.dtsi | 4 ++-- 3 files changed, 5 insertions(+), 5 deletions(-) diff --git a/arch/arm/boot/dts/keystone-k2g.dtsi b/arch/arm/boot/dts/keystone-k2g.dtsi index 63c7cf0c6b6d..7d7b9a8717d9 100644 --- a/arch/arm/boot/dts/keystone-k2g.dtsi +++ b/arch/arm/boot/dts/keystone-k2g.dtsi @@ -90,7 +90,7 @@ }; uart0: serial@02530c00 { - compatible = "ns16550a"; + compatible = "ti,da830-uart", "ns16550a"; current-speed = <115200>; reg-shift = <2>; reg-io-width = <4>; diff --git a/arch/arm/boot/dts/keystone-k2l.dtsi b/arch/arm/boot/dts/keystone-k2l.dtsi index 0c5e74e79ba2..e91633fc0dbd 100644 --- a/arch/arm/boot/dts/keystone-k2l.dtsi +++ b/arch/arm/boot/dts/keystone-k2l.dtsi @@ -35,7 +35,7 @@ /include/ "keystone-k2l-clocks.dtsi" uart2: serial@02348400 { - compatible = "ns16550a"; + compatible = "ti,da830-uart", "ns16550a"; current-speed = <115200>; reg-shift = <2>; reg-io-width = <4>; @@ -45,7 +45,7 @@ }; uart3: serial@02348800 { - compatible = "ns16550a"; + compatible = "ti,da830-uart", "ns16550a"; current-speed = <115200>; reg-shift = <2>; reg-io-width = <4>; diff --git a/arch/arm/boot/dts/keystone.dtsi b/arch/arm/boot/dts/keystone.dtsi index 02708ba2d4f4..9152610255ad 100644 --- a/arch/arm/boot/dts/keystone.dtsi +++ b/arch/arm/boot/dts/keystone.dtsi @@ -98,7 +98,7 @@ /include/ "keystone-clocks.dtsi" uart0: serial@02530c00 { - compatible = "ns16550a"; + compatible = "ti,da830-uart", "ns16550a"; current-speed = <115200>; reg-shift = <2>; reg-io-width = <4>; @@ -108,7 +108,7 @@ }; uart1: serial@02531000 { - compatible = "ns16550a"; + compatible = "ti,da830-uart", "ns16550a"; current-speed = <115200>; reg-shift = <2>; reg-io-width = <4>; From b4d15ba8e7d23b9bfd859f414977d081ef0eed68 Mon Sep 17 00:00:00 2001 From: Suman Anna Date: Sat, 7 Jan 2017 12:33:07 -0800 Subject: [PATCH 02/14] ARM: dts: keystone-k2hk: Add MSM RAM node Add the RAM managed by the Multicore Shared Memory Controller (MSMC) as a mmio-sram node. The 66AK2H SoCs have 6 MB of such memory. Any specific MSM memory range needed by a software module ought to be reserved using an appropriate child node. Signed-off-by: Suman Anna Signed-off-by: Santosh Shilimkar --- arch/arm/boot/dts/keystone-k2hk.dtsi | 8 ++++++++ 1 file changed, 8 insertions(+) diff --git a/arch/arm/boot/dts/keystone-k2hk.dtsi b/arch/arm/boot/dts/keystone-k2hk.dtsi index 8f67fa8df936..39e88d815235 100644 --- a/arch/arm/boot/dts/keystone-k2hk.dtsi +++ b/arch/arm/boot/dts/keystone-k2hk.dtsi @@ -46,6 +46,14 @@ soc { /include/ "keystone-k2hk-clocks.dtsi" + msm_ram: msmram@0c000000 { + compatible = "mmio-sram"; + reg = <0x0c000000 0x600000>; + ranges = <0x0 0x0c000000 0x600000>; + #address-cells = <1>; + #size-cells = <1>; + }; + dspgpio0: keystone_dsp_gpio@02620240 { compatible = "ti,keystone-dsp-gpio"; gpio-controller; From d29db5a159d50762fb71504262985f75353f48f6 Mon Sep 17 00:00:00 2001 From: Suman Anna Date: Sat, 7 Jan 2017 12:33:08 -0800 Subject: [PATCH 03/14] ARM: dts: keystone-k2l: Add MSM RAM node Add the RAM managed by the Multicore Shared Memory Controller (MSMC) as a mmio-sram node. The 66AK2L SoCs have 2 MB of such memory. Any specific MSM memory range needed by a software module ought to be reserved using an appropriate child node. Signed-off-by: Suman Anna Signed-off-by: Santosh Shilimkar --- arch/arm/boot/dts/keystone-k2l.dtsi | 8 ++++++++ 1 file changed, 8 insertions(+) diff --git a/arch/arm/boot/dts/keystone-k2l.dtsi b/arch/arm/boot/dts/keystone-k2l.dtsi index e91633fc0dbd..eab057a7595d 100644 --- a/arch/arm/boot/dts/keystone-k2l.dtsi +++ b/arch/arm/boot/dts/keystone-k2l.dtsi @@ -204,6 +204,14 @@ }; }; + msm_ram: msmram@0c000000 { + compatible = "mmio-sram"; + reg = <0x0c000000 0x200000>; + ranges = <0x0 0x0c000000 0x200000>; + #address-cells = <1>; + #size-cells = <1>; + }; + dspgpio0: keystone_dsp_gpio@02620240 { compatible = "ti,keystone-dsp-gpio"; gpio-controller; From 75eaf87241521c1c94a3ffb150459332d0e924ae Mon Sep 17 00:00:00 2001 From: Suman Anna Date: Sat, 7 Jan 2017 12:33:08 -0800 Subject: [PATCH 04/14] ARM: dts: keystone-k2e: Add MSM RAM node Add the RAM managed by the Multicire Shared Memory Controller (MSMC) as a mmio-sram node. The 66AK2E SoCs have 2 MB of such memory. Any specific MSM memory range needed by a software module ought to be reserved using an appropriate child node. Signed-off-by: Suman Anna Signed-off-by: Santosh Shilimkar --- arch/arm/boot/dts/keystone-k2e.dtsi | 8 ++++++++ 1 file changed, 8 insertions(+) diff --git a/arch/arm/boot/dts/keystone-k2e.dtsi b/arch/arm/boot/dts/keystone-k2e.dtsi index 497c417db5b6..256dcc87f36a 100644 --- a/arch/arm/boot/dts/keystone-k2e.dtsi +++ b/arch/arm/boot/dts/keystone-k2e.dtsi @@ -82,6 +82,14 @@ }; }; + msm_ram: msmram@0c000000 { + compatible = "mmio-sram"; + reg = <0x0c000000 0x200000>; + ranges = <0x0 0x0c000000 0x200000>; + #address-cells = <1>; + #size-cells = <1>; + }; + dspgpio0: keystone_dsp_gpio@02620240 { compatible = "ti,keystone-dsp-gpio"; gpio-controller; From b6f922ab524fb4b2cfedd5c426bf007106cb4c76 Mon Sep 17 00:00:00 2001 From: Suman Anna Date: Sat, 7 Jan 2017 12:33:08 -0800 Subject: [PATCH 05/14] ARM: dts: keystone-k2g: Add MSM RAM node Add the RAM managed by the Multicore Shared Memory Controller (MSMC) as a mmio-sram node. The 66AK2G SoCs have 1 MB of such memory. Any specific MSM memory range needed by a software module ought to be reserved using an appropriate child node. Signed-off-by: Suman Anna Signed-off-by: Santosh Shilimkar --- arch/arm/boot/dts/keystone-k2g.dtsi | 8 ++++++++ 1 file changed, 8 insertions(+) diff --git a/arch/arm/boot/dts/keystone-k2g.dtsi b/arch/arm/boot/dts/keystone-k2g.dtsi index 7d7b9a8717d9..2f75f62c1d0e 100644 --- a/arch/arm/boot/dts/keystone-k2g.dtsi +++ b/arch/arm/boot/dts/keystone-k2g.dtsi @@ -77,6 +77,14 @@ ranges = <0x0 0x0 0x0 0xc0000000>; dma-ranges = <0x80000000 0x8 0x00000000 0x80000000>; + msm_ram: msmram@0c000000 { + compatible = "mmio-sram"; + reg = <0x0c000000 0x100000>; + ranges = <0x0 0x0c000000 0x100000>; + #address-cells = <1>; + #size-cells = <1>; + }; + k2g_pinctrl: pinmux@02621000 { compatible = "pinctrl-single"; reg = <0x02621000 0x410>; From 2e54ecb66229cb91861be236ce58eff823f4bdd1 Mon Sep 17 00:00:00 2001 From: Suman Anna Date: Sat, 7 Jan 2017 12:33:08 -0800 Subject: [PATCH 06/14] ARM: dts: keystone-k2hk: Reserve MSM RAM for boot monitor The Keystone 2 boot monitor uses 32 KB of the MSM RAM @ 0x0c5f0000 on 66AK2H SoCs, so add a reserved child node for the same. This address is aligned to the values used within the latest boot monitor firmware [1] as of commit cf8b431e8b3b ("soc: Move load address to end of MSMC"). [1] git://git.ti.com/processor-firmware/ks2-boot-monitor.git Signed-off-by: Suman Anna Signed-off-by: Santosh Shilimkar --- arch/arm/boot/dts/keystone-k2hk.dtsi | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/arch/arm/boot/dts/keystone-k2hk.dtsi b/arch/arm/boot/dts/keystone-k2hk.dtsi index 39e88d815235..e0780f111537 100644 --- a/arch/arm/boot/dts/keystone-k2hk.dtsi +++ b/arch/arm/boot/dts/keystone-k2hk.dtsi @@ -52,6 +52,10 @@ ranges = <0x0 0x0c000000 0x600000>; #address-cells = <1>; #size-cells = <1>; + + sram-bm@5f0000 { + reg = <0x5f0000 0x8000>; + }; }; dspgpio0: keystone_dsp_gpio@02620240 { From 82d76b6a203c2b36629969d177d456104f5d3451 Mon Sep 17 00:00:00 2001 From: Suman Anna Date: Sat, 7 Jan 2017 12:33:08 -0800 Subject: [PATCH 07/14] ARM: dts: keystone-k2l: Reserve MSM RAM for boot monitor The Keystone 2 boot monitor uses 32 KB of the MSM RAM @ 0x0c1f8000 on 66AK2L SoCs, so add a reserved child node for the same. This address is aligned to the values used within the latest boot monitor firmware [1] as of commit cf8b431e8b3b ("soc: Move load address to end of MSMC"). [1] git://git.ti.com/processor-firmware/ks2-boot-monitor.git Signed-off-by: Suman Anna Signed-off-by: Santosh Shilimkar --- arch/arm/boot/dts/keystone-k2l.dtsi | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/arch/arm/boot/dts/keystone-k2l.dtsi b/arch/arm/boot/dts/keystone-k2l.dtsi index eab057a7595d..e770253794bf 100644 --- a/arch/arm/boot/dts/keystone-k2l.dtsi +++ b/arch/arm/boot/dts/keystone-k2l.dtsi @@ -210,6 +210,10 @@ ranges = <0x0 0x0c000000 0x200000>; #address-cells = <1>; #size-cells = <1>; + + sram-bm@1f8000 { + reg = <0x001f8000 0x8000>; + }; }; dspgpio0: keystone_dsp_gpio@02620240 { From 88bd8224917340127545e504a4d4744636222326 Mon Sep 17 00:00:00 2001 From: Suman Anna Date: Sat, 7 Jan 2017 12:33:08 -0800 Subject: [PATCH 08/14] ARM: dts: keystone-k2e: Reserve MSM RAM for boot monitor The Keystone 2 boot monitor uses 32 KB of the MSM RAM @ 0x0c1f0000 on 66AK2E SoCs, so add a reserved child node for the same. This address is aligned to the values used within the latest boot monitor firmware [1] as of commit cf8b431e8b3b ("soc: Move load address to end of MSMC"). [1] git://git.ti.com/processor-firmware/ks2-boot-monitor.git Signed-off-by: Suman Anna Signed-off-by: Santosh Shilimkar --- arch/arm/boot/dts/keystone-k2e.dtsi | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/arch/arm/boot/dts/keystone-k2e.dtsi b/arch/arm/boot/dts/keystone-k2e.dtsi index 256dcc87f36a..9d1d8a64d10e 100644 --- a/arch/arm/boot/dts/keystone-k2e.dtsi +++ b/arch/arm/boot/dts/keystone-k2e.dtsi @@ -88,6 +88,10 @@ ranges = <0x0 0x0c000000 0x200000>; #address-cells = <1>; #size-cells = <1>; + + sram-bm@1f0000 { + reg = <0x001f0000 0x8000>; + }; }; dspgpio0: keystone_dsp_gpio@02620240 { From b3511c9e525b328effe519ce9e915b80a43eca7d Mon Sep 17 00:00:00 2001 From: Suman Anna Date: Sat, 7 Jan 2017 12:33:08 -0800 Subject: [PATCH 09/14] ARM: dts: keystone-k2g: Reserve MSM RAM for boot monitor The Keystone 2 boot monitor uses 32 KB of the MSM RAM @ 0x0c0f7000 on 66AK2G SoCs, so add a reserved child node for the same. This address is aligned to the values used within the latest boot monitor firmware [1] as of commit cf8b431e8b3b ("soc: Move load address to end of MSMC"). [1] git://git.ti.com/processor-firmware/ks2-boot-monitor.git Signed-off-by: Suman Anna Signed-off-by: Santosh Shilimkar --- arch/arm/boot/dts/keystone-k2g.dtsi | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/arch/arm/boot/dts/keystone-k2g.dtsi b/arch/arm/boot/dts/keystone-k2g.dtsi index 2f75f62c1d0e..10fe0dae2a36 100644 --- a/arch/arm/boot/dts/keystone-k2g.dtsi +++ b/arch/arm/boot/dts/keystone-k2g.dtsi @@ -83,6 +83,10 @@ ranges = <0x0 0x0c000000 0x100000>; #address-cells = <1>; #size-cells = <1>; + + sram-bm@f7000 { + reg = <0x000f7000 0x8000>; + }; }; k2g_pinctrl: pinmux@02621000 { From 32a34441a9bdd95ab79dc018367de89858efda1c Mon Sep 17 00:00:00 2001 From: Murali Karicheri Date: Thu, 19 Jan 2017 09:31:48 -0800 Subject: [PATCH 10/14] ARM: keystone: dts: fix netcp clocks and add names Fix the pa clock to point to the clkpa which has clock rate of 1/3 of PA PLL clock and add clock names. Signed-off-by: Murali Karicheri Signed-off-by: Grygorii Strashko Signed-off-by: Santosh Shilimkar --- arch/arm/boot/dts/keystone-k2e-netcp.dtsi | 3 ++- arch/arm/boot/dts/keystone-k2hk-netcp.dtsi | 3 ++- arch/arm/boot/dts/keystone-k2l-netcp.dtsi | 3 ++- 3 files changed, 6 insertions(+), 3 deletions(-) diff --git a/arch/arm/boot/dts/keystone-k2e-netcp.dtsi b/arch/arm/boot/dts/keystone-k2e-netcp.dtsi index ac990f679725..ba828cb59587 100644 --- a/arch/arm/boot/dts/keystone-k2e-netcp.dtsi +++ b/arch/arm/boot/dts/keystone-k2e-netcp.dtsi @@ -138,7 +138,8 @@ netcp: netcp@24000000 { /* NetCP address range */ ranges = <0 0x24000000 0x1000000>; - clocks = <&papllclk>, <&clkcpgmac>, <&chipclk12>; + clocks = <&clkpa>, <&clkcpgmac>, <&chipclk12>; + clock-names = "pa_clk", "ethss_clk", "cpts"; dma-coherent; ti,navigator-dmas = <&dma_gbe 0>, diff --git a/arch/arm/boot/dts/keystone-k2hk-netcp.dtsi b/arch/arm/boot/dts/keystone-k2hk-netcp.dtsi index f86d6ddb832b..a5ac845464bf 100644 --- a/arch/arm/boot/dts/keystone-k2hk-netcp.dtsi +++ b/arch/arm/boot/dts/keystone-k2hk-netcp.dtsi @@ -155,7 +155,8 @@ netcp: netcp@2000000 { /* NetCP address range */ ranges = <0 0x2000000 0x100000>; - clocks = <&papllclk>, <&clkcpgmac>, <&chipclk12>; + clocks = <&clkpa>, <&clkcpgmac>, <&chipclk12>; + clock-names = "pa_clk", "ethss_clk", "cpts"; dma-coherent; ti,navigator-dmas = <&dma_gbe 22>, diff --git a/arch/arm/boot/dts/keystone-k2l-netcp.dtsi b/arch/arm/boot/dts/keystone-k2l-netcp.dtsi index 5acbd0dcc2ab..b6f26824e83a 100644 --- a/arch/arm/boot/dts/keystone-k2l-netcp.dtsi +++ b/arch/arm/boot/dts/keystone-k2l-netcp.dtsi @@ -137,7 +137,8 @@ netcp: netcp@26000000 { /* NetCP address range */ ranges = <0 0x26000000 0x1000000>; - clocks = <&clkosr>, <&papllclk>, <&clkcpgmac>, <&chipclk12>; + clocks = <&clkpa>, <&clkcpgmac>, <&chipclk12>, <&clkosr>; + clock-names = "pa_clk", "ethss_clk", "cpts", "osr_clk"; dma-coherent; ti,navigator-dmas = <&dma_gbe 0>, From e2dd60f9a5ff224518c8b5c07a95e72e87ee9895 Mon Sep 17 00:00:00 2001 From: Suman Anna Date: Thu, 19 Jan 2017 09:44:11 -0800 Subject: [PATCH 11/14] ARM: dts: keystone: Add PSC node The Power Sleep Controller (PSC) module is responsible for the power and clock management for each of the peripherals present on the SoC. Represent this as a syscon node so that multiple users can leverage it for various functionalities. Signed-off-by: Suman Anna [afd@ti.com: add simple-mfd compatible] Signed-off-by: Andrew F. Davis Signed-off-by: Dave Gerlach Signed-off-by: Santosh Shilimkar --- arch/arm/boot/dts/keystone.dtsi | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/arch/arm/boot/dts/keystone.dtsi b/arch/arm/boot/dts/keystone.dtsi index 9152610255ad..4613c7212251 100644 --- a/arch/arm/boot/dts/keystone.dtsi +++ b/arch/arm/boot/dts/keystone.dtsi @@ -83,6 +83,11 @@ reg = <0x02310000 0x200>; }; + psc: power-sleep-controller@02350000 { + compatible = "syscon", "simple-mfd"; + reg = <0x02350000 0x1000>; + }; + devctrl: device-state-control@02620000 { compatible = "ti,keystone-devctrl", "syscon"; reg = <0x02620000 0x1000>; From e695c71892e711effa3df6ca3c4027fccba53df4 Mon Sep 17 00:00:00 2001 From: Suman Anna Date: Thu, 19 Jan 2017 09:44:11 -0800 Subject: [PATCH 12/14] ARM: dts: keystone-k2hk: Add PSC reset controller node The Power Sleep Controller (PSC) module contains specific memory-mapped registers that can be used to perform reset management using specific bits for the DSPs available on the SoC. The PSC is defined using a syscon node, and the reset functionality is defined using a child syscon reset controller node. Add this syscon reset controller node as well as the reset control data for the resets it supports for the 66AK2H SoCs. Signed-off-by: Andrew F. Davis Signed-off-by: Suman Anna Signed-off-by: Santosh Shilimkar --- arch/arm/boot/dts/keystone-k2hk.dtsi | 20 ++++++++++++++++++++ 1 file changed, 20 insertions(+) diff --git a/arch/arm/boot/dts/keystone-k2hk.dtsi b/arch/arm/boot/dts/keystone-k2hk.dtsi index e0780f111537..69d449430511 100644 --- a/arch/arm/boot/dts/keystone-k2hk.dtsi +++ b/arch/arm/boot/dts/keystone-k2hk.dtsi @@ -8,6 +8,8 @@ * published by the Free Software Foundation. */ +#include + / { compatible = "ti,k2hk", "ti,keystone"; model = "Texas Instruments Keystone 2 Kepler/Hawking SoC"; @@ -58,6 +60,24 @@ }; }; + psc: power-sleep-controller@02350000 { + pscrst: reset-controller { + compatible = "ti,k2hk-pscrst", "ti,syscon-reset"; + #reset-cells = <1>; + + ti,reset-bits = < + 0xa3c 8 0xa3c 8 0x83c 8 (ASSERT_CLEAR | DEASSERT_SET | STATUS_CLEAR) /* 0: dsp0 */ + 0xa40 8 0xa40 8 0x840 8 (ASSERT_CLEAR | DEASSERT_SET | STATUS_CLEAR) /* 1: dsp1 */ + 0xa44 8 0xa44 8 0x844 8 (ASSERT_CLEAR | DEASSERT_SET | STATUS_CLEAR) /* 2: dsp2 */ + 0xa48 8 0xa48 8 0x848 8 (ASSERT_CLEAR | DEASSERT_SET | STATUS_CLEAR) /* 3: dsp3 */ + 0xa4c 8 0xa4c 8 0x84c 8 (ASSERT_CLEAR | DEASSERT_SET | STATUS_CLEAR) /* 4: dsp4 */ + 0xa50 8 0xa50 8 0x850 8 (ASSERT_CLEAR | DEASSERT_SET | STATUS_CLEAR) /* 5: dsp5 */ + 0xa54 8 0xa54 8 0x854 8 (ASSERT_CLEAR | DEASSERT_SET | STATUS_CLEAR) /* 6: dsp6 */ + 0xa58 8 0xa58 8 0x858 8 (ASSERT_CLEAR | DEASSERT_SET | STATUS_CLEAR) /* 7: dsp7 */ + >; + }; + }; + dspgpio0: keystone_dsp_gpio@02620240 { compatible = "ti,keystone-dsp-gpio"; gpio-controller; From 2ae4dad3523be2779a5844348c8bf84d1c9c1584 Mon Sep 17 00:00:00 2001 From: Suman Anna Date: Thu, 19 Jan 2017 09:44:11 -0800 Subject: [PATCH 13/14] ARM: dts: keystone-k2l: Add PSC reset controller node The Power Sleep Controller (PSC) module contains specific memory-mapped registers that can be used to perform reset management using specific bits for the DSPs available on the SoC. The PSC is defined using a syscon node, and the reset functionality is defined using a child syscon reset controller node. Add this syscon reset controller node as well as the reset control data for the resets it supports for the 66AK2L SoCs. Signed-off-by: Andrew F. Davis Signed-off-by: Suman Anna Signed-off-by: Santosh Shilimkar --- arch/arm/boot/dts/keystone-k2l.dtsi | 16 ++++++++++++++++ 1 file changed, 16 insertions(+) diff --git a/arch/arm/boot/dts/keystone-k2l.dtsi b/arch/arm/boot/dts/keystone-k2l.dtsi index e770253794bf..b58e7ebc0919 100644 --- a/arch/arm/boot/dts/keystone-k2l.dtsi +++ b/arch/arm/boot/dts/keystone-k2l.dtsi @@ -8,6 +8,8 @@ * published by the Free Software Foundation. */ +#include + / { compatible = "ti,k2l", "ti,keystone"; model = "Texas Instruments Keystone 2 Lamarr SoC"; @@ -216,6 +218,20 @@ }; }; + psc: power-sleep-controller@02350000 { + pscrst: reset-controller { + compatible = "ti,k2l-pscrst", "ti,syscon-reset"; + #reset-cells = <1>; + + ti,reset-bits = < + 0xa3c 8 0xa3c 8 0x83c 8 (ASSERT_CLEAR | DEASSERT_SET | STATUS_CLEAR) /* 0: dsp0 */ + 0xa40 8 0xa40 8 0x840 8 (ASSERT_CLEAR | DEASSERT_SET | STATUS_CLEAR) /* 1: dsp1 */ + 0xa44 8 0xa44 8 0x844 8 (ASSERT_CLEAR | DEASSERT_SET | STATUS_CLEAR) /* 2: dsp2 */ + 0xa48 8 0xa48 8 0x848 8 (ASSERT_CLEAR | DEASSERT_SET | STATUS_CLEAR) /* 3: dsp3 */ + >; + }; + }; + dspgpio0: keystone_dsp_gpio@02620240 { compatible = "ti,keystone-dsp-gpio"; gpio-controller; From 0623013ca629d311be2114314ddaf220604493d3 Mon Sep 17 00:00:00 2001 From: Suman Anna Date: Thu, 19 Jan 2017 09:44:11 -0800 Subject: [PATCH 14/14] ARM: dts: keystone-k2e: Add PSC reset controller node The Power Sleep Controller (PSC) module contains specific memory-mapped registers that can be used to perform reset management using specific bits for the DSPs available on the SoC. The PSC is defined using a syscon node, and the reset functionality is defined using a child syscon reset controller node. Add this syscon reset controller node as well as the reset control data for the resets it supports for the 66AK2E SoCs. Signed-off-by: Andrew F. Davis Signed-off-by: Suman Anna Signed-off-by: Santosh Shilimkar --- arch/arm/boot/dts/keystone-k2e.dtsi | 13 +++++++++++++ 1 file changed, 13 insertions(+) diff --git a/arch/arm/boot/dts/keystone-k2e.dtsi b/arch/arm/boot/dts/keystone-k2e.dtsi index 9d1d8a64d10e..0dd4cdd6d40c 100644 --- a/arch/arm/boot/dts/keystone-k2e.dtsi +++ b/arch/arm/boot/dts/keystone-k2e.dtsi @@ -8,6 +8,8 @@ * published by the Free Software Foundation. */ +#include + / { compatible = "ti,k2e", "ti,keystone"; model = "Texas Instruments Keystone 2 Edison SoC"; @@ -94,6 +96,17 @@ }; }; + psc: power-sleep-controller@02350000 { + pscrst: reset-controller { + compatible = "ti,k2e-pscrst", "ti,syscon-reset"; + #reset-cells = <1>; + + ti,reset-bits = < + 0xa3c 8 0xa3c 8 0x83c 8 (ASSERT_CLEAR | DEASSERT_SET | STATUS_CLEAR) /* 0: dsp0 */ + >; + }; + }; + dspgpio0: keystone_dsp_gpio@02620240 { compatible = "ti,keystone-dsp-gpio"; gpio-controller;