fpga: dfl: map feature mmio resources in their own feature drivers
This patch makes preparation for modularization of DFL sub feature drivers. DFL based FPGA devices may contain some IP blocks which are already supported by kernel, most of them are supported by platform device drivers. We could create platform devices for these IP blocks and get them supported by these drivers. An important issue is that platform device drivers usually requests mmio resources on probe. But now DFL mmio is mapped in DFL bus driver (e.g. dfl-pci) as a whole region. Then platform device drivers for sub features can't request their own mmio resources again. This is what the patch trying to resolve. This patch changes the DFL enumeration. DFL bus driver will unmap mmio resources after first step enumeration and pass enumeration info to DFL framework. Then DFL framework will map the mmio resources again, do 2nd step enumeration, and also unmap the mmio resources. In this way, sub feature drivers could then request their own mmio resources as needed. An exception is that mmio resource of FIU headers are still mapped in DFL bus driver. The FIU headers have some fundamental functions (sriov set, port enable/disable) needed for DFL bus devices and other sub features. They should not be unmapped as long as DFL bus device is alive. Signed-off-by: Xu Yilun <yilun.xu@intel.com> Signed-off-by: Wu Hao <hao.wu@intel.com> Signed-off-by: Matthew Gerlach <matthew.gerlach@linux.intel.com> Signed-off-by: Russ Weight <russell.h.weight@intel.com> Reviewed-by: Tom Rix <trix@redhat.com> Acked-by: Wu Hao <hao.wu@intel.com> Signed-off-by: Moritz Fischer <mdf@kernel.org>
This commit is contained in:
Xu Yilun
Moritz Fischer
parent
4e772ab86b
commit
89eb35e810
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@ -31,12 +31,12 @@ struct cci_drvdata {
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struct dfl_fpga_cdev *cdev; /* container device */
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};
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static void __iomem *cci_pci_ioremap_bar(struct pci_dev *pcidev, int bar)
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static void __iomem *cci_pci_ioremap_bar0(struct pci_dev *pcidev)
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{
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if (pcim_iomap_regions(pcidev, BIT(bar), DRV_NAME))
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if (pcim_iomap_regions(pcidev, BIT(0), DRV_NAME))
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return NULL;
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return pcim_iomap_table(pcidev)[bar];
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return pcim_iomap_table(pcidev)[0];
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}
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static int cci_pci_alloc_irq(struct pci_dev *pcidev)
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@ -156,8 +156,8 @@ static int cci_enumerate_feature_devs(struct pci_dev *pcidev)
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goto irq_free_exit;
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}
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/* start to find Device Feature List from Bar 0 */
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base = cci_pci_ioremap_bar(pcidev, 0);
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/* start to find Device Feature List in Bar 0 */
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base = cci_pci_ioremap_bar0(pcidev);
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if (!base) {
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ret = -ENOMEM;
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goto irq_free_exit;
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@ -172,7 +172,7 @@ static int cci_enumerate_feature_devs(struct pci_dev *pcidev)
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start = pci_resource_start(pcidev, 0);
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len = pci_resource_len(pcidev, 0);
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dfl_fpga_enum_info_add_dfl(info, start, len, base);
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dfl_fpga_enum_info_add_dfl(info, start, len);
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/*
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* find more Device Feature Lists (e.g. Ports) per information
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@ -196,26 +196,24 @@ static int cci_enumerate_feature_devs(struct pci_dev *pcidev)
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*/
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bar = FIELD_GET(FME_PORT_OFST_BAR_ID, v);
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offset = FIELD_GET(FME_PORT_OFST_DFH_OFST, v);
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base = cci_pci_ioremap_bar(pcidev, bar);
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if (!base)
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continue;
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start = pci_resource_start(pcidev, bar) + offset;
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len = pci_resource_len(pcidev, bar) - offset;
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dfl_fpga_enum_info_add_dfl(info, start, len,
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base + offset);
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dfl_fpga_enum_info_add_dfl(info, start, len);
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}
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} else if (dfl_feature_is_port(base)) {
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start = pci_resource_start(pcidev, 0);
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len = pci_resource_len(pcidev, 0);
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dfl_fpga_enum_info_add_dfl(info, start, len, base);
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dfl_fpga_enum_info_add_dfl(info, start, len);
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} else {
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ret = -ENODEV;
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goto irq_free_exit;
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}
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/* release I/O mappings for next step enumeration */
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pcim_iounmap_regions(pcidev, BIT(0));
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/* start enumeration with prepared enumeration information */
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cdev = dfl_fpga_feature_devs_enumerate(info);
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if (IS_ERR(cdev)) {
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@ -250,6 +250,8 @@ int dfl_fpga_check_port_id(struct platform_device *pdev, void *pport_id)
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}
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EXPORT_SYMBOL_GPL(dfl_fpga_check_port_id);
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#define is_header_feature(feature) ((feature)->id == FEATURE_ID_FIU_HEADER)
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/**
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* dfl_fpga_dev_feature_uinit - uinit for sub features of dfl feature device
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* @pdev: feature device.
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@ -273,8 +275,22 @@ static int dfl_feature_instance_init(struct platform_device *pdev,
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struct dfl_feature *feature,
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struct dfl_feature_driver *drv)
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{
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void __iomem *base;
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int ret = 0;
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if (!is_header_feature(feature)) {
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base = devm_platform_ioremap_resource(pdev,
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feature->resource_index);
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if (IS_ERR(base)) {
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dev_err(&pdev->dev,
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"ioremap failed for feature 0x%x!\n",
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feature->id);
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return PTR_ERR(base);
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}
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feature->ioaddr = base;
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}
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if (drv->ops->init) {
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ret = drv->ops->init(pdev, feature);
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if (ret)
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@ -427,7 +443,9 @@ EXPORT_SYMBOL_GPL(dfl_fpga_dev_ops_unregister);
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* @irq_table: Linux IRQ numbers for all irqs, indexed by local irq index of
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* this device.
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* @feature_dev: current feature device.
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* @ioaddr: header register region address of feature device in enumeration.
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* @ioaddr: header register region address of current FIU in enumeration.
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* @start: register resource start of current FIU.
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* @len: max register resource length of current FIU.
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* @sub_features: a sub features linked list for feature device in enumeration.
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* @feature_num: number of sub features for feature device in enumeration.
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*/
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@ -439,6 +457,8 @@ struct build_feature_devs_info {
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struct platform_device *feature_dev;
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void __iomem *ioaddr;
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resource_size_t start;
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resource_size_t len;
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struct list_head sub_features;
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int feature_num;
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};
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@ -484,10 +504,7 @@ static int build_info_commit_dev(struct build_feature_devs_info *binfo)
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struct dfl_feature_platform_data *pdata;
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struct dfl_feature_info *finfo, *p;
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enum dfl_id_type type;
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int ret, index = 0;
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if (!fdev)
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return 0;
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int ret, index = 0, res_idx = 0;
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type = feature_dev_id_type(fdev);
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if (WARN_ON_ONCE(type >= DFL_ID_MAX))
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@ -530,16 +547,32 @@ static int build_info_commit_dev(struct build_feature_devs_info *binfo)
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/* fill features and resource information for feature dev */
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list_for_each_entry_safe(finfo, p, &binfo->sub_features, node) {
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struct dfl_feature *feature = &pdata->features[index];
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struct dfl_feature *feature = &pdata->features[index++];
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struct dfl_feature_irq_ctx *ctx;
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unsigned int i;
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/* save resource information for each feature */
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feature->dev = fdev;
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feature->id = finfo->fid;
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feature->resource_index = index;
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feature->ioaddr = finfo->ioaddr;
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fdev->resource[index++] = finfo->mmio_res;
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/*
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* the FIU header feature has some fundamental functions (sriov
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* set, port enable/disable) needed for the dfl bus device and
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* other sub features. So its mmio resource should be mapped by
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* DFL bus device. And we should not assign it to feature
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* devices (dfl-fme/afu) again.
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*/
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if (is_header_feature(feature)) {
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feature->resource_index = -1;
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feature->ioaddr =
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devm_ioremap_resource(binfo->dev,
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&finfo->mmio_res);
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if (IS_ERR(feature->ioaddr))
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return PTR_ERR(feature->ioaddr);
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} else {
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feature->resource_index = res_idx;
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fdev->resource[res_idx++] = finfo->mmio_res;
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}
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if (finfo->nr_irqs) {
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ctx = devm_kcalloc(binfo->dev, finfo->nr_irqs,
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@ -582,19 +615,13 @@ static int build_info_commit_dev(struct build_feature_devs_info *binfo)
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static int
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build_info_create_dev(struct build_feature_devs_info *binfo,
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enum dfl_id_type type, void __iomem *ioaddr)
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enum dfl_id_type type)
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{
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struct platform_device *fdev;
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int ret;
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if (type >= DFL_ID_MAX)
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return -EINVAL;
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/* we will create a new device, commit current device first */
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ret = build_info_commit_dev(binfo);
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if (ret)
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return ret;
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/*
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* we use -ENODEV as the initialization indicator which indicates
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* whether the id need to be reclaimed
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@ -605,7 +632,7 @@ build_info_create_dev(struct build_feature_devs_info *binfo,
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binfo->feature_dev = fdev;
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binfo->feature_num = 0;
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binfo->ioaddr = ioaddr;
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INIT_LIST_HEAD(&binfo->sub_features);
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fdev->id = dfl_id_alloc(type, &fdev->dev);
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@ -747,18 +774,17 @@ static int parse_feature_irqs(struct build_feature_devs_info *binfo,
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*/
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static int
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create_feature_instance(struct build_feature_devs_info *binfo,
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struct dfl_fpga_enum_dfl *dfl, resource_size_t ofst,
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resource_size_t size, u16 fid)
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resource_size_t ofst, resource_size_t size, u16 fid)
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{
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unsigned int irq_base, nr_irqs;
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struct dfl_feature_info *finfo;
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int ret;
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/* read feature size and id if inputs are invalid */
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size = size ? size : feature_size(dfl->ioaddr + ofst);
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fid = fid ? fid : feature_id(dfl->ioaddr + ofst);
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size = size ? size : feature_size(binfo->ioaddr + ofst);
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fid = fid ? fid : feature_id(binfo->ioaddr + ofst);
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if (dfl->len - ofst < size)
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if (binfo->len - ofst < size)
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return -EINVAL;
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ret = parse_feature_irqs(binfo, ofst, fid, &irq_base, &nr_irqs);
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@ -770,12 +796,11 @@ create_feature_instance(struct build_feature_devs_info *binfo,
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return -ENOMEM;
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finfo->fid = fid;
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finfo->mmio_res.start = dfl->start + ofst;
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finfo->mmio_res.start = binfo->start + ofst;
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finfo->mmio_res.end = finfo->mmio_res.start + size - 1;
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finfo->mmio_res.flags = IORESOURCE_MEM;
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finfo->irq_base = irq_base;
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finfo->nr_irqs = nr_irqs;
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finfo->ioaddr = dfl->ioaddr + ofst;
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list_add_tail(&finfo->node, &binfo->sub_features);
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binfo->feature_num++;
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@ -784,7 +809,6 @@ create_feature_instance(struct build_feature_devs_info *binfo,
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}
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static int parse_feature_port_afu(struct build_feature_devs_info *binfo,
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struct dfl_fpga_enum_dfl *dfl,
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resource_size_t ofst)
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{
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u64 v = readq(binfo->ioaddr + PORT_HDR_CAP);
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@ -792,21 +816,22 @@ static int parse_feature_port_afu(struct build_feature_devs_info *binfo,
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WARN_ON(!size);
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return create_feature_instance(binfo, dfl, ofst, size, FEATURE_ID_AFU);
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return create_feature_instance(binfo, ofst, size, FEATURE_ID_AFU);
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}
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#define is_feature_dev_detected(binfo) (!!(binfo)->feature_dev)
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static int parse_feature_afu(struct build_feature_devs_info *binfo,
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struct dfl_fpga_enum_dfl *dfl,
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resource_size_t ofst)
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{
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if (!binfo->feature_dev) {
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if (!is_feature_dev_detected(binfo)) {
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dev_err(binfo->dev, "this AFU does not belong to any FIU.\n");
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return -EINVAL;
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}
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switch (feature_dev_id_type(binfo->feature_dev)) {
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case PORT_ID:
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return parse_feature_port_afu(binfo, dfl, ofst);
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return parse_feature_port_afu(binfo, ofst);
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default:
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dev_info(binfo->dev, "AFU belonging to FIU %s is not supported yet.\n",
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binfo->feature_dev->name);
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@ -815,8 +840,39 @@ static int parse_feature_afu(struct build_feature_devs_info *binfo,
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return 0;
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}
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static int build_info_prepare(struct build_feature_devs_info *binfo,
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resource_size_t start, resource_size_t len)
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{
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struct device *dev = binfo->dev;
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void __iomem *ioaddr;
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if (!devm_request_mem_region(dev, start, len, dev_name(dev))) {
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dev_err(dev, "request region fail, start:%pa, len:%pa\n",
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&start, &len);
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return -EBUSY;
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}
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ioaddr = devm_ioremap(dev, start, len);
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if (!ioaddr) {
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dev_err(dev, "ioremap region fail, start:%pa, len:%pa\n",
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&start, &len);
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return -ENOMEM;
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}
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binfo->start = start;
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binfo->len = len;
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binfo->ioaddr = ioaddr;
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return 0;
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}
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static void build_info_complete(struct build_feature_devs_info *binfo)
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{
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devm_iounmap(binfo->dev, binfo->ioaddr);
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devm_release_mem_region(binfo->dev, binfo->start, binfo->len);
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}
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static int parse_feature_fiu(struct build_feature_devs_info *binfo,
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struct dfl_fpga_enum_dfl *dfl,
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resource_size_t ofst)
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{
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int ret = 0;
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@ -824,27 +880,39 @@ static int parse_feature_fiu(struct build_feature_devs_info *binfo,
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u16 id;
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u64 v;
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v = readq(dfl->ioaddr + ofst + DFH);
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if (is_feature_dev_detected(binfo)) {
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build_info_complete(binfo);
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ret = build_info_commit_dev(binfo);
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if (ret)
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return ret;
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ret = build_info_prepare(binfo, binfo->start + ofst,
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binfo->len - ofst);
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if (ret)
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return ret;
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}
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v = readq(binfo->ioaddr + DFH);
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id = FIELD_GET(DFH_ID, v);
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/* create platform device for dfl feature dev */
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ret = build_info_create_dev(binfo, dfh_id_to_type(id),
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dfl->ioaddr + ofst);
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ret = build_info_create_dev(binfo, dfh_id_to_type(id));
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if (ret)
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return ret;
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ret = create_feature_instance(binfo, dfl, ofst, 0, 0);
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ret = create_feature_instance(binfo, 0, 0, 0);
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if (ret)
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return ret;
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/*
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* find and parse FIU's child AFU via its NEXT_AFU register.
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* please note that only Port has valid NEXT_AFU pointer per spec.
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*/
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v = readq(dfl->ioaddr + ofst + NEXT_AFU);
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v = readq(binfo->ioaddr + NEXT_AFU);
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offset = FIELD_GET(NEXT_AFU_NEXT_DFH_OFST, v);
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if (offset)
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return parse_feature_afu(binfo, dfl, ofst + offset);
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return parse_feature_afu(binfo, offset);
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dev_dbg(binfo->dev, "No AFUs detected on FIU %d\n", id);
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@ -852,41 +920,39 @@ static int parse_feature_fiu(struct build_feature_devs_info *binfo,
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}
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static int parse_feature_private(struct build_feature_devs_info *binfo,
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struct dfl_fpga_enum_dfl *dfl,
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resource_size_t ofst)
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{
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if (!binfo->feature_dev) {
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if (!is_feature_dev_detected(binfo)) {
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dev_err(binfo->dev, "the private feature 0x%x does not belong to any AFU.\n",
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feature_id(dfl->ioaddr + ofst));
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feature_id(binfo->ioaddr + ofst));
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return -EINVAL;
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}
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return create_feature_instance(binfo, dfl, ofst, 0, 0);
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return create_feature_instance(binfo, ofst, 0, 0);
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}
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/**
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* parse_feature - parse a feature on given device feature list
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*
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* @binfo: build feature devices information.
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* @dfl: device feature list to parse
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* @ofst: offset to feature header on this device feature list
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* @ofst: offset to current FIU header
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*/
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static int parse_feature(struct build_feature_devs_info *binfo,
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struct dfl_fpga_enum_dfl *dfl, resource_size_t ofst)
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resource_size_t ofst)
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{
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u64 v;
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u32 type;
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v = readq(dfl->ioaddr + ofst + DFH);
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v = readq(binfo->ioaddr + ofst + DFH);
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type = FIELD_GET(DFH_TYPE, v);
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switch (type) {
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case DFH_TYPE_AFU:
|
||||
return parse_feature_afu(binfo, dfl, ofst);
|
||||
return parse_feature_afu(binfo, ofst);
|
||||
case DFH_TYPE_PRIVATE:
|
||||
return parse_feature_private(binfo, dfl, ofst);
|
||||
return parse_feature_private(binfo, ofst);
|
||||
case DFH_TYPE_FIU:
|
||||
return parse_feature_fiu(binfo, dfl, ofst);
|
||||
return parse_feature_fiu(binfo, ofst);
|
||||
default:
|
||||
dev_info(binfo->dev,
|
||||
"Feature Type %x is not supported.\n", type);
|
||||
|
|
@ -896,14 +962,17 @@ static int parse_feature(struct build_feature_devs_info *binfo,
|
|||
}
|
||||
|
||||
static int parse_feature_list(struct build_feature_devs_info *binfo,
|
||||
struct dfl_fpga_enum_dfl *dfl)
|
||||
resource_size_t start, resource_size_t len)
|
||||
{
|
||||
void __iomem *start = dfl->ioaddr;
|
||||
void __iomem *end = dfl->ioaddr + dfl->len;
|
||||
resource_size_t end = start + len;
|
||||
int ret = 0;
|
||||
u32 ofst = 0;
|
||||
u64 v;
|
||||
|
||||
ret = build_info_prepare(binfo, start, len);
|
||||
if (ret)
|
||||
return ret;
|
||||
|
||||
/* walk through the device feature list via DFH's next DFH pointer. */
|
||||
for (; start < end; start += ofst) {
|
||||
if (end - start < DFH_SIZE) {
|
||||
|
|
@ -911,11 +980,11 @@ static int parse_feature_list(struct build_feature_devs_info *binfo,
|
|||
return -EINVAL;
|
||||
}
|
||||
|
||||
ret = parse_feature(binfo, dfl, start - dfl->ioaddr);
|
||||
ret = parse_feature(binfo, start - binfo->start);
|
||||
if (ret)
|
||||
return ret;
|
||||
|
||||
v = readq(start + DFH);
|
||||
v = readq(binfo->ioaddr + start - binfo->start + DFH);
|
||||
ofst = FIELD_GET(DFH_NEXT_HDR_OFST, v);
|
||||
|
||||
/* stop parsing if EOL(End of List) is set or offset is 0 */
|
||||
|
|
@ -924,7 +993,12 @@ static int parse_feature_list(struct build_feature_devs_info *binfo,
|
|||
}
|
||||
|
||||
/* commit current feature device when reach the end of list */
|
||||
return build_info_commit_dev(binfo);
|
||||
build_info_complete(binfo);
|
||||
|
||||
if (is_feature_dev_detected(binfo))
|
||||
ret = build_info_commit_dev(binfo);
|
||||
|
||||
return ret;
|
||||
}
|
||||
|
||||
struct dfl_fpga_enum_info *dfl_fpga_enum_info_alloc(struct device *dev)
|
||||
|
|
@ -977,7 +1051,6 @@ EXPORT_SYMBOL_GPL(dfl_fpga_enum_info_free);
|
|||
* @info: ptr to dfl_fpga_enum_info
|
||||
* @start: mmio resource address of the device feature list.
|
||||
* @len: mmio resource length of the device feature list.
|
||||
* @ioaddr: mapped mmio resource address of the device feature list.
|
||||
*
|
||||
* One FPGA device may have one or more Device Feature Lists (DFLs), use this
|
||||
* function to add information of each DFL to common data structure for next
|
||||
|
|
@ -986,8 +1059,7 @@ EXPORT_SYMBOL_GPL(dfl_fpga_enum_info_free);
|
|||
* Return: 0 on success, negative error code otherwise.
|
||||
*/
|
||||
int dfl_fpga_enum_info_add_dfl(struct dfl_fpga_enum_info *info,
|
||||
resource_size_t start, resource_size_t len,
|
||||
void __iomem *ioaddr)
|
||||
resource_size_t start, resource_size_t len)
|
||||
{
|
||||
struct dfl_fpga_enum_dfl *dfl;
|
||||
|
||||
|
|
@ -997,7 +1069,6 @@ int dfl_fpga_enum_info_add_dfl(struct dfl_fpga_enum_info *info,
|
|||
|
||||
dfl->start = start;
|
||||
dfl->len = len;
|
||||
dfl->ioaddr = ioaddr;
|
||||
|
||||
list_add_tail(&dfl->node, &info->dfls);
|
||||
|
||||
|
|
@ -1120,7 +1191,7 @@ dfl_fpga_feature_devs_enumerate(struct dfl_fpga_enum_info *info)
|
|||
* Lists.
|
||||
*/
|
||||
list_for_each_entry(dfl, &info->dfls, node) {
|
||||
ret = parse_feature_list(binfo, dfl);
|
||||
ret = parse_feature_list(binfo, dfl->start, dfl->len);
|
||||
if (ret) {
|
||||
remove_feature_devs(cdev);
|
||||
build_info_free(binfo);
|
||||
|
|
|
|||
|
|
@ -441,22 +441,17 @@ struct dfl_fpga_enum_info {
|
|||
*
|
||||
* @start: base address of this device feature list.
|
||||
* @len: size of this device feature list.
|
||||
* @ioaddr: mapped base address of this device feature list.
|
||||
* @node: node in list of device feature lists.
|
||||
*/
|
||||
struct dfl_fpga_enum_dfl {
|
||||
resource_size_t start;
|
||||
resource_size_t len;
|
||||
|
||||
void __iomem *ioaddr;
|
||||
|
||||
struct list_head node;
|
||||
};
|
||||
|
||||
struct dfl_fpga_enum_info *dfl_fpga_enum_info_alloc(struct device *dev);
|
||||
int dfl_fpga_enum_info_add_dfl(struct dfl_fpga_enum_info *info,
|
||||
resource_size_t start, resource_size_t len,
|
||||
void __iomem *ioaddr);
|
||||
resource_size_t start, resource_size_t len);
|
||||
int dfl_fpga_enum_info_add_irq(struct dfl_fpga_enum_info *info,
|
||||
unsigned int nr_irqs, int *irq_table);
|
||||
void dfl_fpga_enum_info_free(struct dfl_fpga_enum_info *info);
|
||||
|
|
|
|||
Loading…
Reference in New Issue