Merge branch 'brcm-asp-2.0-support'
Justin Chen says: ==================== Brcm ASP 2.0 Ethernet Controller Add support for the Broadcom ASP 2.0 Ethernet controller which is first introduced with 72165. ==================== Signed-off-by: David S. Miller <davem@davemloft.net>
This commit is contained in:
David S. Miller
commit
89e970ea7f
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@ -0,0 +1,155 @@
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# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
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%YAML 1.2
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---
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$id: http://devicetree.org/schemas/net/brcm,asp-v2.0.yaml#
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$schema: http://devicetree.org/meta-schemas/core.yaml#
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title: Broadcom ASP 2.0 Ethernet controller
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maintainers:
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- Justin Chen <justin.chen@broadcom.com>
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- Florian Fainelli <florian.fainelli@broadcom.com>
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description: Broadcom Ethernet controller first introduced with 72165
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properties:
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compatible:
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oneOf:
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- items:
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- enum:
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- brcm,bcm74165-asp
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- const: brcm,asp-v2.1
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- items:
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- enum:
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- brcm,bcm72165-asp
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- const: brcm,asp-v2.0
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"#address-cells":
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const: 1
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"#size-cells":
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const: 1
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reg:
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maxItems: 1
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ranges: true
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interrupts:
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minItems: 1
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items:
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- description: RX/TX interrupt
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- description: Port 0 Wake-on-LAN
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- description: Port 1 Wake-on-LAN
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clocks:
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maxItems: 1
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ethernet-ports:
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type: object
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properties:
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"#address-cells":
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const: 1
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"#size-cells":
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const: 0
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patternProperties:
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"^port@[0-9]+$":
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type: object
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$ref: ethernet-controller.yaml#
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unevaluatedProperties: false
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properties:
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reg:
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maxItems: 1
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description: Port number
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brcm,channel:
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$ref: /schemas/types.yaml#/definitions/uint32
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description: |
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ASP Channel Number
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The depacketizer channel that consumes packets from
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the unimac/port.
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required:
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- reg
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- brcm,channel
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additionalProperties: false
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patternProperties:
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"^mdio@[0-9a-f]+$":
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type: object
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$ref: brcm,unimac-mdio.yaml
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description:
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ASP internal UniMAC MDIO bus
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required:
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- compatible
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- reg
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- interrupts
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- clocks
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- ranges
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additionalProperties: false
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examples:
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- |
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#include <dt-bindings/interrupt-controller/irq.h>
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#include <dt-bindings/interrupt-controller/arm-gic.h>
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ethernet@9c00000 {
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compatible = "brcm,bcm72165-asp", "brcm,asp-v2.0";
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reg = <0x9c00000 0x1fff14>;
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interrupts = <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>;
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ranges = <0x0 0x9c00000 0x1fff14>;
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clocks = <&scmi 14>;
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#address-cells = <1>;
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#size-cells = <1>;
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mdio@c614 {
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compatible = "brcm,asp-v2.0-mdio";
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reg = <0xc614 0x8>;
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reg-names = "mdio";
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#address-cells = <1>;
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#size-cells = <0>;
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phy0: ethernet-phy@1 {
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reg = <1>;
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};
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};
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mdio@ce14 {
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compatible = "brcm,asp-v2.0-mdio";
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reg = <0xce14 0x8>;
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reg-names = "mdio";
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#address-cells = <1>;
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#size-cells = <0>;
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phy1: ethernet-phy@1 {
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reg = <1>;
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};
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};
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ethernet-ports {
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#address-cells = <1>;
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#size-cells = <0>;
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port@0 {
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reg = <0>;
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brcm,channel = <8>;
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phy-mode = "rgmii";
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phy-handle = <&phy0>;
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};
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port@1 {
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reg = <1>;
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brcm,channel = <9>;
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phy-mode = "rgmii";
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phy-handle = <&phy1>;
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};
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};
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};
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@ -22,6 +22,8 @@ properties:
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- brcm,genet-mdio-v3
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- brcm,genet-mdio-v4
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- brcm,genet-mdio-v5
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- brcm,asp-v2.0-mdio
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- brcm,asp-v2.1-mdio
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- brcm,unimac-mdio
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reg:
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|
|
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@ -4145,6 +4145,15 @@ F: drivers/net/mdio/mdio-bcm-unimac.c
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F: include/linux/platform_data/bcmgenet.h
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F: include/linux/platform_data/mdio-bcm-unimac.h
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BROADCOM ASP 2.0 ETHERNET DRIVER
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M: Justin Chen <justin.chen@broadcom.com>
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M: Florian Fainelli <florian.fainelli@broadcom.com>
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L: bcm-kernel-feedback-list@broadcom.com
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L: netdev@vger.kernel.org
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S: Supported
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F: Documentation/devicetree/bindings/net/brcm,asp-v2.0.yaml
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F: drivers/net/ethernet/broadcom/asp2/
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BROADCOM IPROC ARM ARCHITECTURE
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M: Ray Jui <rjui@broadcom.com>
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M: Scott Branden <sbranden@broadcom.com>
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|
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@ -255,4 +255,15 @@ config BNXT_HWMON
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Say Y if you want to expose the thermal sensor data on NetXtreme-C/E
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devices, via the hwmon sysfs interface.
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config BCMASP
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tristate "Broadcom ASP 2.0 Ethernet support"
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default ARCH_BRCMSTB
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depends on OF
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select MII
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select PHYLIB
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select MDIO_BCM_UNIMAC
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help
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This configuration enables the Broadcom ASP 2.0 Ethernet controller
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driver which is present in Broadcom STB SoCs such as 72165.
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endif # NET_VENDOR_BROADCOM
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@ -17,3 +17,4 @@ obj-$(CONFIG_BGMAC_BCMA) += bgmac-bcma.o bgmac-bcma-mdio.o
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obj-$(CONFIG_BGMAC_PLATFORM) += bgmac-platform.o
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obj-$(CONFIG_SYSTEMPORT) += bcmsysport.o
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obj-$(CONFIG_BNXT) += bnxt/
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obj-$(CONFIG_BCMASP) += asp2/
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@ -0,0 +1,2 @@
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obj-$(CONFIG_BCMASP) += bcm-asp.o
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bcm-asp-objs := bcmasp.o bcmasp_intf.o bcmasp_ethtool.o
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File diff suppressed because it is too large
Load Diff
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@ -0,0 +1,586 @@
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/* SPDX-License-Identifier: GPL-2.0 */
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#ifndef __BCMASP_H
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#define __BCMASP_H
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#include <linux/netdevice.h>
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#include <linux/phy.h>
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#include <linux/io-64-nonatomic-hi-lo.h>
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#include <uapi/linux/ethtool.h>
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#define ASP_INTR2_OFFSET 0x1000
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#define ASP_INTR2_STATUS 0x0
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#define ASP_INTR2_SET 0x4
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#define ASP_INTR2_CLEAR 0x8
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#define ASP_INTR2_MASK_STATUS 0xc
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#define ASP_INTR2_MASK_SET 0x10
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#define ASP_INTR2_MASK_CLEAR 0x14
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#define ASP_INTR2_RX_ECH(intr) BIT(intr)
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#define ASP_INTR2_TX_DESC(intr) BIT((intr) + 14)
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#define ASP_INTR2_UMC0_WAKE BIT(22)
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#define ASP_INTR2_UMC1_WAKE BIT(28)
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#define ASP_WAKEUP_INTR2_OFFSET 0x1200
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#define ASP_WAKEUP_INTR2_STATUS 0x0
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#define ASP_WAKEUP_INTR2_SET 0x4
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#define ASP_WAKEUP_INTR2_CLEAR 0x8
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#define ASP_WAKEUP_INTR2_MASK_STATUS 0xc
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#define ASP_WAKEUP_INTR2_MASK_SET 0x10
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#define ASP_WAKEUP_INTR2_MASK_CLEAR 0x14
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#define ASP_WAKEUP_INTR2_MPD_0 BIT(0)
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#define ASP_WAKEUP_INTR2_MPD_1 BIT(1)
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#define ASP_WAKEUP_INTR2_FILT_0 BIT(2)
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#define ASP_WAKEUP_INTR2_FILT_1 BIT(3)
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#define ASP_WAKEUP_INTR2_FW BIT(4)
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#define ASP_TX_ANALYTICS_OFFSET 0x4c000
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#define ASP_TX_ANALYTICS_CTRL 0x0
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#define ASP_RX_ANALYTICS_OFFSET 0x98000
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#define ASP_RX_ANALYTICS_CTRL 0x0
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#define ASP_RX_CTRL_OFFSET 0x9f000
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#define ASP_RX_CTRL_UMAC_0_FRAME_COUNT 0x8
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#define ASP_RX_CTRL_UMAC_1_FRAME_COUNT 0xc
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#define ASP_RX_CTRL_FB_0_FRAME_COUNT 0x14
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#define ASP_RX_CTRL_FB_1_FRAME_COUNT 0x18
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#define ASP_RX_CTRL_FB_8_FRAME_COUNT 0x1c
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/* asp2.1 diverges offsets here */
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/* ASP2.0 */
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#define ASP_RX_CTRL_FB_OUT_FRAME_COUNT 0x20
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#define ASP_RX_CTRL_FB_FILT_OUT_FRAME_COUNT 0x24
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#define ASP_RX_CTRL_FLUSH 0x28
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#define ASP_CTRL_UMAC0_FLUSH_MASK (BIT(0) | BIT(12))
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#define ASP_CTRL_UMAC1_FLUSH_MASK (BIT(1) | BIT(13))
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#define ASP_CTRL_SPB_FLUSH_MASK (BIT(8) | BIT(20))
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#define ASP_RX_CTRL_FB_RX_FIFO_DEPTH 0x30
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/* ASP2.1 */
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#define ASP_RX_CTRL_FB_9_FRAME_COUNT_2_1 0x20
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#define ASP_RX_CTRL_FB_10_FRAME_COUNT_2_1 0x24
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#define ASP_RX_CTRL_FB_OUT_FRAME_COUNT_2_1 0x28
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#define ASP_RX_CTRL_FB_FILT_OUT_FRAME_COUNT_2_1 0x2c
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#define ASP_RX_CTRL_FLUSH_2_1 0x30
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#define ASP_RX_CTRL_FB_RX_FIFO_DEPTH_2_1 0x38
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#define ASP_RX_FILTER_OFFSET 0x80000
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#define ASP_RX_FILTER_BLK_CTRL 0x0
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#define ASP_RX_FILTER_OPUT_EN BIT(0)
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#define ASP_RX_FILTER_MDA_EN BIT(1)
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#define ASP_RX_FILTER_LNR_MD BIT(2)
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#define ASP_RX_FILTER_GEN_WK_EN BIT(3)
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#define ASP_RX_FILTER_GEN_WK_CLR BIT(4)
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#define ASP_RX_FILTER_NT_FLT_EN BIT(5)
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#define ASP_RX_FILTER_MDA_CFG(sel) (((sel) * 0x14) + 0x100)
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#define ASP_RX_FILTER_MDA_CFG_EN_SHIFT 8
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#define ASP_RX_FILTER_MDA_CFG_UMC_SEL(sel) ((sel) > 1 ? BIT(17) : \
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BIT((sel) + 9))
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#define ASP_RX_FILTER_MDA_PAT_H(sel) (((sel) * 0x14) + 0x104)
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#define ASP_RX_FILTER_MDA_PAT_L(sel) (((sel) * 0x14) + 0x108)
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#define ASP_RX_FILTER_MDA_MSK_H(sel) (((sel) * 0x14) + 0x10c)
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#define ASP_RX_FILTER_MDA_MSK_L(sel) (((sel) * 0x14) + 0x110)
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#define ASP_RX_FILTER_MDA_CFG(sel) (((sel) * 0x14) + 0x100)
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#define ASP_RX_FILTER_MDA_PAT_H(sel) (((sel) * 0x14) + 0x104)
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#define ASP_RX_FILTER_MDA_PAT_L(sel) (((sel) * 0x14) + 0x108)
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#define ASP_RX_FILTER_MDA_MSK_H(sel) (((sel) * 0x14) + 0x10c)
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#define ASP_RX_FILTER_MDA_MSK_L(sel) (((sel) * 0x14) + 0x110)
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#define ASP_RX_FILTER_NET_CFG(sel) (((sel) * 0xa04) + 0x400)
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#define ASP_RX_FILTER_NET_CFG_CH(sel) ((sel) << 0)
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#define ASP_RX_FILTER_NET_CFG_EN BIT(9)
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#define ASP_RX_FILTER_NET_CFG_L2_EN BIT(10)
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#define ASP_RX_FILTER_NET_CFG_L3_EN BIT(11)
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#define ASP_RX_FILTER_NET_CFG_L4_EN BIT(12)
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#define ASP_RX_FILTER_NET_CFG_L3_FRM(sel) ((sel) << 13)
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#define ASP_RX_FILTER_NET_CFG_L4_FRM(sel) ((sel) << 15)
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#define ASP_RX_FILTER_NET_CFG_UMC(sel) BIT((sel) + 19)
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#define ASP_RX_FILTER_NET_CFG_DMA_EN BIT(27)
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#define ASP_RX_FILTER_NET_OFFSET_MAX 32
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#define ASP_RX_FILTER_NET_PAT(sel, block, off) \
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(((sel) * 0xa04) + ((block) * 0x200) + (off) + 0x600)
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#define ASP_RX_FILTER_NET_MASK(sel, block, off) \
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(((sel) * 0xa04) + ((block) * 0x200) + (off) + 0x700)
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||||
|
||||
#define ASP_RX_FILTER_NET_OFFSET(sel) (((sel) * 0xa04) + 0xe00)
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||||
#define ASP_RX_FILTER_NET_OFFSET_L2(val) ((val) << 0)
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||||
#define ASP_RX_FILTER_NET_OFFSET_L3_0(val) ((val) << 8)
|
||||
#define ASP_RX_FILTER_NET_OFFSET_L3_1(val) ((val) << 16)
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||||
#define ASP_RX_FILTER_NET_OFFSET_L4(val) ((val) << 24)
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||||
|
||||
enum asp_rx_net_filter_block {
|
||||
ASP_RX_FILTER_NET_L2 = 0,
|
||||
ASP_RX_FILTER_NET_L3_0,
|
||||
ASP_RX_FILTER_NET_L3_1,
|
||||
ASP_RX_FILTER_NET_L4,
|
||||
ASP_RX_FILTER_NET_BLOCK_MAX
|
||||
};
|
||||
|
||||
#define ASP_EDPKT_OFFSET 0x9c000
|
||||
#define ASP_EDPKT_ENABLE 0x4
|
||||
#define ASP_EDPKT_ENABLE_EN BIT(0)
|
||||
#define ASP_EDPKT_HDR_CFG 0xc
|
||||
#define ASP_EDPKT_HDR_SZ_SHIFT 2
|
||||
#define ASP_EDPKT_HDR_SZ_32 0
|
||||
#define ASP_EDPKT_HDR_SZ_64 1
|
||||
#define ASP_EDPKT_HDR_SZ_96 2
|
||||
#define ASP_EDPKT_HDR_SZ_128 3
|
||||
#define ASP_EDPKT_BURST_BUF_PSCAL_TOUT 0x10
|
||||
#define ASP_EDPKT_BURST_BUF_WRITE_TOUT 0x14
|
||||
#define ASP_EDPKT_BURST_BUF_READ_TOUT 0x18
|
||||
#define ASP_EDPKT_RX_TS_COUNTER 0x38
|
||||
#define ASP_EDPKT_ENDI 0x48
|
||||
#define ASP_EDPKT_ENDI_DESC_SHIFT 8
|
||||
#define ASP_EDPKT_ENDI_NO_BT_SWP 0
|
||||
#define ASP_EDPKT_ENDI_BT_SWP_WD 1
|
||||
#define ASP_EDPKT_RX_PKT_CNT 0x138
|
||||
#define ASP_EDPKT_HDR_EXTR_CNT 0x13c
|
||||
#define ASP_EDPKT_HDR_OUT_CNT 0x140
|
||||
|
||||
#define ASP_CTRL 0x101000
|
||||
#define ASP_CTRL_ASP_SW_INIT 0x04
|
||||
#define ASP_CTRL_ASP_SW_INIT_ACPUSS_CORE BIT(0)
|
||||
#define ASP_CTRL_ASP_SW_INIT_ASP_TX BIT(1)
|
||||
#define ASP_CTRL_ASP_SW_INIT_AS_RX BIT(2)
|
||||
#define ASP_CTRL_ASP_SW_INIT_ASP_RGMII_UMAC0 BIT(3)
|
||||
#define ASP_CTRL_ASP_SW_INIT_ASP_RGMII_UMAC1 BIT(4)
|
||||
#define ASP_CTRL_ASP_SW_INIT_ASP_XMEMIF BIT(5)
|
||||
#define ASP_CTRL_CLOCK_CTRL 0x04
|
||||
#define ASP_CTRL_CLOCK_CTRL_ASP_TX_DISABLE BIT(0)
|
||||
#define ASP_CTRL_CLOCK_CTRL_ASP_RX_DISABLE BIT(1)
|
||||
#define ASP_CTRL_CLOCK_CTRL_ASP_RGMII_SHIFT 2
|
||||
#define ASP_CTRL_CLOCK_CTRL_ASP_RGMII_MASK (0x7 << ASP_CTRL_CLOCK_CTRL_ASP_RGMII_SHIFT)
|
||||
#define ASP_CTRL_CLOCK_CTRL_ASP_RGMII_DIS(x) BIT(ASP_CTRL_CLOCK_CTRL_ASP_RGMII_SHIFT + (x))
|
||||
#define ASP_CTRL_CLOCK_CTRL_ASP_ALL_DISABLE GENMASK(4, 0)
|
||||
#define ASP_CTRL_CORE_CLOCK_SELECT 0x08
|
||||
#define ASP_CTRL_CORE_CLOCK_SELECT_MAIN BIT(0)
|
||||
#define ASP_CTRL_SCRATCH_0 0x0c
|
||||
|
||||
struct bcmasp_tx_cb {
|
||||
struct sk_buff *skb;
|
||||
unsigned int bytes_sent;
|
||||
bool last;
|
||||
|
||||
DEFINE_DMA_UNMAP_ADDR(dma_addr);
|
||||
DEFINE_DMA_UNMAP_LEN(dma_len);
|
||||
};
|
||||
|
||||
struct bcmasp_res {
|
||||
/* Per interface resources */
|
||||
/* Port */
|
||||
void __iomem *umac;
|
||||
void __iomem *umac2fb;
|
||||
void __iomem *rgmii;
|
||||
|
||||
/* TX slowpath/configuration */
|
||||
void __iomem *tx_spb_ctrl;
|
||||
void __iomem *tx_spb_top;
|
||||
void __iomem *tx_epkt_core;
|
||||
void __iomem *tx_pause_ctrl;
|
||||
};
|
||||
|
||||
#define DESC_ADDR(x) ((x) & GENMASK_ULL(39, 0))
|
||||
#define DESC_FLAGS(x) ((x) & GENMASK_ULL(63, 40))
|
||||
|
||||
struct bcmasp_desc {
|
||||
u64 buf;
|
||||
#define DESC_CHKSUM BIT_ULL(40)
|
||||
#define DESC_CRC_ERR BIT_ULL(41)
|
||||
#define DESC_RX_SYM_ERR BIT_ULL(42)
|
||||
#define DESC_NO_OCT_ALN BIT_ULL(43)
|
||||
#define DESC_PKT_TRUC BIT_ULL(44)
|
||||
/* 39:0 (TX/RX) bits 0-39 of buf addr
|
||||
* 40 (RX) checksum
|
||||
* 41 (RX) crc_error
|
||||
* 42 (RX) rx_symbol_error
|
||||
* 43 (RX) non_octet_aligned
|
||||
* 44 (RX) pkt_truncated
|
||||
* 45 Reserved
|
||||
* 56:46 (RX) mac_filter_id
|
||||
* 60:57 (RX) rx_port_num (0-unicmac0, 1-unimac1)
|
||||
* 61 Reserved
|
||||
* 63:62 (TX) forward CRC, overwrite CRC
|
||||
*/
|
||||
u32 size;
|
||||
u32 flags;
|
||||
#define DESC_INT_EN BIT(0)
|
||||
#define DESC_SOF BIT(1)
|
||||
#define DESC_EOF BIT(2)
|
||||
#define DESC_EPKT_CMD BIT(3)
|
||||
#define DESC_SCRAM_ST BIT(8)
|
||||
#define DESC_SCRAM_END BIT(9)
|
||||
#define DESC_PCPP BIT(10)
|
||||
#define DESC_PPPP BIT(11)
|
||||
/* 0 (TX) tx_int_en
|
||||
* 1 (TX/RX) SOF
|
||||
* 2 (TX/RX) EOF
|
||||
* 3 (TX) epkt_command
|
||||
* 6:4 (TX) PA
|
||||
* 7 (TX) pause at desc end
|
||||
* 8 (TX) scram_start
|
||||
* 9 (TX) scram_end
|
||||
* 10 (TX) PCPP
|
||||
* 11 (TX) PPPP
|
||||
* 14:12 Reserved
|
||||
* 15 (TX) pid ch Valid
|
||||
* 19:16 (TX) data_pkt_type
|
||||
* 32:20 (TX) pid_channel (RX) nw_filter_id
|
||||
*/
|
||||
};
|
||||
|
||||
struct bcmasp_intf;
|
||||
|
||||
struct bcmasp_intf_stats64 {
|
||||
/* Rx Stats */
|
||||
u64_stats_t rx_packets;
|
||||
u64_stats_t rx_bytes;
|
||||
u64_stats_t rx_errors;
|
||||
u64_stats_t rx_dropped;
|
||||
u64_stats_t rx_crc_errs;
|
||||
u64_stats_t rx_sym_errs;
|
||||
|
||||
/* Tx Stats*/
|
||||
u64_stats_t tx_packets;
|
||||
u64_stats_t tx_bytes;
|
||||
|
||||
struct u64_stats_sync syncp;
|
||||
};
|
||||
|
||||
struct bcmasp_mib_counters {
|
||||
u32 edpkt_ts;
|
||||
u32 edpkt_rx_pkt_cnt;
|
||||
u32 edpkt_hdr_ext_cnt;
|
||||
u32 edpkt_hdr_out_cnt;
|
||||
u32 umac_frm_cnt;
|
||||
u32 fb_frm_cnt;
|
||||
u32 fb_rx_fifo_depth;
|
||||
u32 fb_out_frm_cnt;
|
||||
u32 fb_filt_out_frm_cnt;
|
||||
u32 alloc_rx_skb_failed;
|
||||
u32 tx_dma_failed;
|
||||
u32 mc_filters_full_cnt;
|
||||
u32 uc_filters_full_cnt;
|
||||
u32 filters_combine_cnt;
|
||||
u32 promisc_filters_cnt;
|
||||
u32 tx_realloc_offload_failed;
|
||||
u32 tx_timeout_cnt;
|
||||
};
|
||||
|
||||
struct bcmasp_intf_ops {
|
||||
unsigned long (*rx_desc_read)(struct bcmasp_intf *intf);
|
||||
void (*rx_buffer_write)(struct bcmasp_intf *intf, dma_addr_t addr);
|
||||
void (*rx_desc_write)(struct bcmasp_intf *intf, dma_addr_t addr);
|
||||
unsigned long (*tx_read)(struct bcmasp_intf *intf);
|
||||
void (*tx_write)(struct bcmasp_intf *intf, dma_addr_t addr);
|
||||
};
|
||||
|
||||
struct bcmasp_priv;
|
||||
|
||||
struct bcmasp_intf {
|
||||
struct list_head list;
|
||||
struct net_device *ndev;
|
||||
struct bcmasp_priv *parent;
|
||||
|
||||
/* ASP Ch */
|
||||
int channel;
|
||||
int port;
|
||||
const struct bcmasp_intf_ops *ops;
|
||||
|
||||
/* Used for splitting shared resources */
|
||||
int index;
|
||||
|
||||
struct napi_struct tx_napi;
|
||||
/* TX ring, starts on a new cacheline boundary */
|
||||
void __iomem *tx_spb_dma;
|
||||
int tx_spb_index;
|
||||
int tx_spb_clean_index;
|
||||
struct bcmasp_desc *tx_spb_cpu;
|
||||
dma_addr_t tx_spb_dma_addr;
|
||||
dma_addr_t tx_spb_dma_valid;
|
||||
dma_addr_t tx_spb_dma_read;
|
||||
struct bcmasp_tx_cb *tx_cbs;
|
||||
|
||||
/* RX ring, starts on a new cacheline boundary */
|
||||
void __iomem *rx_edpkt_cfg;
|
||||
void __iomem *rx_edpkt_dma;
|
||||
int rx_edpkt_index;
|
||||
int rx_buf_order;
|
||||
struct bcmasp_desc *rx_edpkt_cpu;
|
||||
dma_addr_t rx_edpkt_dma_addr;
|
||||
dma_addr_t rx_edpkt_dma_read;
|
||||
|
||||
/* RX buffer prefetcher ring*/
|
||||
void *rx_ring_cpu;
|
||||
dma_addr_t rx_ring_dma;
|
||||
dma_addr_t rx_ring_dma_valid;
|
||||
struct napi_struct rx_napi;
|
||||
|
||||
struct bcmasp_res res;
|
||||
unsigned int crc_fwd;
|
||||
|
||||
/* PHY device */
|
||||
struct device_node *phy_dn;
|
||||
struct device_node *ndev_dn;
|
||||
phy_interface_t phy_interface;
|
||||
bool internal_phy;
|
||||
int old_pause;
|
||||
int old_link;
|
||||
int old_duplex;
|
||||
|
||||
u32 msg_enable;
|
||||
|
||||
/* Statistics */
|
||||
struct bcmasp_intf_stats64 stats64;
|
||||
struct bcmasp_mib_counters mib;
|
||||
|
||||
u32 wolopts;
|
||||
u8 sopass[SOPASS_MAX];
|
||||
/* Used if per intf wol irq */
|
||||
int wol_irq;
|
||||
unsigned int wol_irq_enabled:1;
|
||||
|
||||
struct ethtool_eee eee;
|
||||
};
|
||||
|
||||
#define NUM_NET_FILTERS 32
|
||||
struct bcmasp_net_filter {
|
||||
struct ethtool_rx_flow_spec fs;
|
||||
|
||||
bool claimed;
|
||||
bool wake_filter;
|
||||
|
||||
int port;
|
||||
unsigned int hw_index;
|
||||
};
|
||||
|
||||
#define NUM_MDA_FILTERS 32
|
||||
struct bcmasp_mda_filter {
|
||||
/* Current owner of this filter */
|
||||
int port;
|
||||
bool en;
|
||||
u8 addr[ETH_ALEN];
|
||||
u8 mask[ETH_ALEN];
|
||||
};
|
||||
|
||||
struct bcmasp_hw_info {
|
||||
u32 rx_ctrl_flush;
|
||||
u32 umac2fb;
|
||||
u32 rx_ctrl_fb_out_frame_count;
|
||||
u32 rx_ctrl_fb_filt_out_frame_count;
|
||||
u32 rx_ctrl_fb_rx_fifo_depth;
|
||||
};
|
||||
|
||||
struct bcmasp_plat_data {
|
||||
void (*init_wol)(struct bcmasp_priv *priv);
|
||||
void (*enable_wol)(struct bcmasp_intf *intf, bool en);
|
||||
void (*destroy_wol)(struct bcmasp_priv *priv);
|
||||
struct bcmasp_hw_info *hw_info;
|
||||
};
|
||||
|
||||
struct bcmasp_priv {
|
||||
struct platform_device *pdev;
|
||||
struct clk *clk;
|
||||
|
||||
int irq;
|
||||
u32 irq_mask;
|
||||
|
||||
/* Used if shared wol irq */
|
||||
struct mutex wol_lock;
|
||||
int wol_irq;
|
||||
unsigned long wol_irq_enabled_mask;
|
||||
|
||||
void (*init_wol)(struct bcmasp_priv *priv);
|
||||
void (*enable_wol)(struct bcmasp_intf *intf, bool en);
|
||||
void (*destroy_wol)(struct bcmasp_priv *priv);
|
||||
|
||||
void __iomem *base;
|
||||
struct bcmasp_hw_info *hw_info;
|
||||
|
||||
struct list_head intfs;
|
||||
|
||||
struct bcmasp_mda_filter mda_filters[NUM_MDA_FILTERS];
|
||||
|
||||
/* MAC destination address filters lock */
|
||||
spinlock_t mda_lock;
|
||||
|
||||
/* Protects accesses to ASP_CTRL_CLOCK_CTRL */
|
||||
spinlock_t clk_lock;
|
||||
|
||||
struct bcmasp_net_filter net_filters[NUM_NET_FILTERS];
|
||||
|
||||
/* Network filter lock */
|
||||
struct mutex net_lock;
|
||||
};
|
||||
|
||||
static inline unsigned long bcmasp_intf_rx_desc_read(struct bcmasp_intf *intf)
|
||||
{
|
||||
return intf->ops->rx_desc_read(intf);
|
||||
}
|
||||
|
||||
static inline void bcmasp_intf_rx_buffer_write(struct bcmasp_intf *intf,
|
||||
dma_addr_t addr)
|
||||
{
|
||||
intf->ops->rx_buffer_write(intf, addr);
|
||||
}
|
||||
|
||||
static inline void bcmasp_intf_rx_desc_write(struct bcmasp_intf *intf,
|
||||
dma_addr_t addr)
|
||||
{
|
||||
intf->ops->rx_desc_write(intf, addr);
|
||||
}
|
||||
|
||||
static inline unsigned long bcmasp_intf_tx_read(struct bcmasp_intf *intf)
|
||||
{
|
||||
return intf->ops->tx_read(intf);
|
||||
}
|
||||
|
||||
static inline void bcmasp_intf_tx_write(struct bcmasp_intf *intf,
|
||||
dma_addr_t addr)
|
||||
{
|
||||
intf->ops->tx_write(intf, addr);
|
||||
}
|
||||
|
||||
#define __BCMASP_IO_MACRO(name, m) \
|
||||
static inline u32 name##_rl(struct bcmasp_intf *intf, u32 off) \
|
||||
{ \
|
||||
u32 reg = readl_relaxed(intf->m + off); \
|
||||
return reg; \
|
||||
} \
|
||||
static inline void name##_wl(struct bcmasp_intf *intf, u32 val, u32 off)\
|
||||
{ \
|
||||
writel_relaxed(val, intf->m + off); \
|
||||
}
|
||||
|
||||
#define BCMASP_IO_MACRO(name) __BCMASP_IO_MACRO(name, res.name)
|
||||
#define BCMASP_FP_IO_MACRO(name) __BCMASP_IO_MACRO(name, name)
|
||||
|
||||
BCMASP_IO_MACRO(umac);
|
||||
BCMASP_IO_MACRO(umac2fb);
|
||||
BCMASP_IO_MACRO(rgmii);
|
||||
BCMASP_FP_IO_MACRO(tx_spb_dma);
|
||||
BCMASP_IO_MACRO(tx_spb_ctrl);
|
||||
BCMASP_IO_MACRO(tx_spb_top);
|
||||
BCMASP_IO_MACRO(tx_epkt_core);
|
||||
BCMASP_IO_MACRO(tx_pause_ctrl);
|
||||
BCMASP_FP_IO_MACRO(rx_edpkt_dma);
|
||||
BCMASP_FP_IO_MACRO(rx_edpkt_cfg);
|
||||
|
||||
#define __BCMASP_FP_IO_MACRO_Q(name, m) \
|
||||
static inline u64 name##_rq(struct bcmasp_intf *intf, u32 off) \
|
||||
{ \
|
||||
u64 reg = readq_relaxed(intf->m + off); \
|
||||
return reg; \
|
||||
} \
|
||||
static inline void name##_wq(struct bcmasp_intf *intf, u64 val, u32 off)\
|
||||
{ \
|
||||
writeq_relaxed(val, intf->m + off); \
|
||||
}
|
||||
|
||||
#define BCMASP_FP_IO_MACRO_Q(name) __BCMASP_FP_IO_MACRO_Q(name, name)
|
||||
|
||||
BCMASP_FP_IO_MACRO_Q(tx_spb_dma);
|
||||
BCMASP_FP_IO_MACRO_Q(rx_edpkt_dma);
|
||||
BCMASP_FP_IO_MACRO_Q(rx_edpkt_cfg);
|
||||
|
||||
#define PKT_OFFLOAD_NOP (0 << 28)
|
||||
#define PKT_OFFLOAD_HDR_OP (1 << 28)
|
||||
#define PKT_OFFLOAD_HDR_WRBACK BIT(19)
|
||||
#define PKT_OFFLOAD_HDR_COUNT(x) ((x) << 16)
|
||||
#define PKT_OFFLOAD_HDR_SIZE_1(x) ((x) << 4)
|
||||
#define PKT_OFFLOAD_HDR_SIZE_2(x) (x)
|
||||
#define PKT_OFFLOAD_HDR2_SIZE_2(x) ((x) << 24)
|
||||
#define PKT_OFFLOAD_HDR2_SIZE_3(x) ((x) << 12)
|
||||
#define PKT_OFFLOAD_HDR2_SIZE_4(x) (x)
|
||||
#define PKT_OFFLOAD_EPKT_OP (2 << 28)
|
||||
#define PKT_OFFLOAD_EPKT_WRBACK BIT(23)
|
||||
#define PKT_OFFLOAD_EPKT_IP(x) ((x) << 21)
|
||||
#define PKT_OFFLOAD_EPKT_TP(x) ((x) << 19)
|
||||
#define PKT_OFFLOAD_EPKT_LEN(x) ((x) << 16)
|
||||
#define PKT_OFFLOAD_EPKT_CSUM_L3 BIT(15)
|
||||
#define PKT_OFFLOAD_EPKT_CSUM_L2 BIT(14)
|
||||
#define PKT_OFFLOAD_EPKT_ID(x) ((x) << 12)
|
||||
#define PKT_OFFLOAD_EPKT_SEQ(x) ((x) << 10)
|
||||
#define PKT_OFFLOAD_EPKT_TS(x) ((x) << 8)
|
||||
#define PKT_OFFLOAD_EPKT_BLOC(x) (x)
|
||||
#define PKT_OFFLOAD_END_OP (7 << 28)
|
||||
|
||||
struct bcmasp_pkt_offload {
|
||||
__be32 nop;
|
||||
__be32 header;
|
||||
__be32 header2;
|
||||
__be32 epkt;
|
||||
__be32 end;
|
||||
};
|
||||
|
||||
#define BCMASP_CORE_IO_MACRO(name, offset) \
|
||||
static inline u32 name##_core_rl(struct bcmasp_priv *priv, \
|
||||
u32 off) \
|
||||
{ \
|
||||
u32 reg = readl_relaxed(priv->base + (offset) + off); \
|
||||
return reg; \
|
||||
} \
|
||||
static inline void name##_core_wl(struct bcmasp_priv *priv, \
|
||||
u32 val, u32 off) \
|
||||
{ \
|
||||
writel_relaxed(val, priv->base + (offset) + off); \
|
||||
}
|
||||
|
||||
BCMASP_CORE_IO_MACRO(intr2, ASP_INTR2_OFFSET);
|
||||
BCMASP_CORE_IO_MACRO(wakeup_intr2, ASP_WAKEUP_INTR2_OFFSET);
|
||||
BCMASP_CORE_IO_MACRO(tx_analytics, ASP_TX_ANALYTICS_OFFSET);
|
||||
BCMASP_CORE_IO_MACRO(rx_analytics, ASP_RX_ANALYTICS_OFFSET);
|
||||
BCMASP_CORE_IO_MACRO(rx_ctrl, ASP_RX_CTRL_OFFSET);
|
||||
BCMASP_CORE_IO_MACRO(rx_filter, ASP_RX_FILTER_OFFSET);
|
||||
BCMASP_CORE_IO_MACRO(rx_edpkt, ASP_EDPKT_OFFSET);
|
||||
BCMASP_CORE_IO_MACRO(ctrl, ASP_CTRL);
|
||||
|
||||
struct bcmasp_intf *bcmasp_interface_create(struct bcmasp_priv *priv,
|
||||
struct device_node *ndev_dn, int i);
|
||||
|
||||
void bcmasp_interface_destroy(struct bcmasp_intf *intf);
|
||||
|
||||
void bcmasp_enable_tx_irq(struct bcmasp_intf *intf, int en);
|
||||
|
||||
void bcmasp_enable_rx_irq(struct bcmasp_intf *intf, int en);
|
||||
|
||||
void bcmasp_flush_rx_port(struct bcmasp_intf *intf);
|
||||
|
||||
extern const struct ethtool_ops bcmasp_ethtool_ops;
|
||||
|
||||
int bcmasp_interface_suspend(struct bcmasp_intf *intf);
|
||||
|
||||
int bcmasp_interface_resume(struct bcmasp_intf *intf);
|
||||
|
||||
void bcmasp_set_promisc(struct bcmasp_intf *intf, bool en);
|
||||
|
||||
void bcmasp_set_allmulti(struct bcmasp_intf *intf, bool en);
|
||||
|
||||
void bcmasp_set_broad(struct bcmasp_intf *intf, bool en);
|
||||
|
||||
void bcmasp_set_oaddr(struct bcmasp_intf *intf, const unsigned char *addr,
|
||||
bool en);
|
||||
|
||||
int bcmasp_set_en_mda_filter(struct bcmasp_intf *intf, unsigned char *addr,
|
||||
unsigned char *mask);
|
||||
|
||||
void bcmasp_disable_all_filters(struct bcmasp_intf *intf);
|
||||
|
||||
void bcmasp_core_clock_set_intf(struct bcmasp_intf *intf, bool en);
|
||||
|
||||
struct bcmasp_net_filter *bcmasp_netfilt_get_init(struct bcmasp_intf *intf,
|
||||
int loc, bool wake_filter,
|
||||
bool init);
|
||||
|
||||
bool bcmasp_netfilt_check_dup(struct bcmasp_intf *intf,
|
||||
struct ethtool_rx_flow_spec *fs);
|
||||
|
||||
void bcmasp_netfilt_release(struct bcmasp_intf *intf,
|
||||
struct bcmasp_net_filter *nfilt);
|
||||
|
||||
int bcmasp_netfilt_get_active(struct bcmasp_intf *intf);
|
||||
|
||||
void bcmasp_netfilt_get_all_active(struct bcmasp_intf *intf, u32 *rule_locs,
|
||||
u32 *rule_cnt);
|
||||
|
||||
void bcmasp_netfilt_suspend(struct bcmasp_intf *intf);
|
||||
|
||||
void bcmasp_eee_enable_set(struct bcmasp_intf *intf, bool enable);
|
||||
#endif
|
||||
|
|
@ -0,0 +1,503 @@
|
|||
// SPDX-License-Identifier: GPL-2.0
|
||||
#define pr_fmt(fmt) "bcmasp_ethtool: " fmt
|
||||
|
||||
#include <asm-generic/unaligned.h>
|
||||
#include <linux/ethtool.h>
|
||||
#include <linux/netdevice.h>
|
||||
#include <linux/platform_device.h>
|
||||
|
||||
#include "bcmasp.h"
|
||||
#include "bcmasp_intf_defs.h"
|
||||
|
||||
enum bcmasp_stat_type {
|
||||
BCMASP_STAT_RX_EDPKT,
|
||||
BCMASP_STAT_RX_CTRL,
|
||||
BCMASP_STAT_RX_CTRL_PER_INTF,
|
||||
BCMASP_STAT_SOFT,
|
||||
};
|
||||
|
||||
struct bcmasp_stats {
|
||||
char stat_string[ETH_GSTRING_LEN];
|
||||
enum bcmasp_stat_type type;
|
||||
u32 reg_offset;
|
||||
};
|
||||
|
||||
#define STAT_BCMASP_SOFT_MIB(str) { \
|
||||
.stat_string = str, \
|
||||
.type = BCMASP_STAT_SOFT, \
|
||||
}
|
||||
|
||||
#define STAT_BCMASP_OFFSET(str, _type, offset) { \
|
||||
.stat_string = str, \
|
||||
.type = _type, \
|
||||
.reg_offset = offset, \
|
||||
}
|
||||
|
||||
#define STAT_BCMASP_RX_EDPKT(str, offset) \
|
||||
STAT_BCMASP_OFFSET(str, BCMASP_STAT_RX_EDPKT, offset)
|
||||
#define STAT_BCMASP_RX_CTRL(str, offset) \
|
||||
STAT_BCMASP_OFFSET(str, BCMASP_STAT_RX_CTRL, offset)
|
||||
#define STAT_BCMASP_RX_CTRL_PER_INTF(str, offset) \
|
||||
STAT_BCMASP_OFFSET(str, BCMASP_STAT_RX_CTRL_PER_INTF, offset)
|
||||
|
||||
/* Must match the order of struct bcmasp_mib_counters */
|
||||
static const struct bcmasp_stats bcmasp_gstrings_stats[] = {
|
||||
/* EDPKT counters */
|
||||
STAT_BCMASP_RX_EDPKT("RX Time Stamp", ASP_EDPKT_RX_TS_COUNTER),
|
||||
STAT_BCMASP_RX_EDPKT("RX PKT Count", ASP_EDPKT_RX_PKT_CNT),
|
||||
STAT_BCMASP_RX_EDPKT("RX PKT Buffered", ASP_EDPKT_HDR_EXTR_CNT),
|
||||
STAT_BCMASP_RX_EDPKT("RX PKT Pushed to DRAM", ASP_EDPKT_HDR_OUT_CNT),
|
||||
/* ASP RX control */
|
||||
STAT_BCMASP_RX_CTRL_PER_INTF("Frames From Unimac",
|
||||
ASP_RX_CTRL_UMAC_0_FRAME_COUNT),
|
||||
STAT_BCMASP_RX_CTRL_PER_INTF("Frames From Port",
|
||||
ASP_RX_CTRL_FB_0_FRAME_COUNT),
|
||||
STAT_BCMASP_RX_CTRL_PER_INTF("RX Buffer FIFO Depth",
|
||||
ASP_RX_CTRL_FB_RX_FIFO_DEPTH),
|
||||
STAT_BCMASP_RX_CTRL("Frames Out(Buffer)",
|
||||
ASP_RX_CTRL_FB_OUT_FRAME_COUNT),
|
||||
STAT_BCMASP_RX_CTRL("Frames Out(Filters)",
|
||||
ASP_RX_CTRL_FB_FILT_OUT_FRAME_COUNT),
|
||||
/* Software maintained statistics */
|
||||
STAT_BCMASP_SOFT_MIB("RX SKB Alloc Failed"),
|
||||
STAT_BCMASP_SOFT_MIB("TX DMA Failed"),
|
||||
STAT_BCMASP_SOFT_MIB("Multicast Filters Full"),
|
||||
STAT_BCMASP_SOFT_MIB("Unicast Filters Full"),
|
||||
STAT_BCMASP_SOFT_MIB("MDA Filters Combined"),
|
||||
STAT_BCMASP_SOFT_MIB("Promisc Filter Set"),
|
||||
STAT_BCMASP_SOFT_MIB("TX Realloc For Offload Failed"),
|
||||
STAT_BCMASP_SOFT_MIB("Tx Timeout Count"),
|
||||
};
|
||||
|
||||
#define BCMASP_STATS_LEN ARRAY_SIZE(bcmasp_gstrings_stats)
|
||||
|
||||
static u16 bcmasp_stat_fixup_offset(struct bcmasp_intf *intf,
|
||||
const struct bcmasp_stats *s)
|
||||
{
|
||||
struct bcmasp_priv *priv = intf->parent;
|
||||
|
||||
if (!strcmp("Frames Out(Buffer)", s->stat_string))
|
||||
return priv->hw_info->rx_ctrl_fb_out_frame_count;
|
||||
|
||||
if (!strcmp("Frames Out(Filters)", s->stat_string))
|
||||
return priv->hw_info->rx_ctrl_fb_filt_out_frame_count;
|
||||
|
||||
if (!strcmp("RX Buffer FIFO Depth", s->stat_string))
|
||||
return priv->hw_info->rx_ctrl_fb_rx_fifo_depth;
|
||||
|
||||
return s->reg_offset;
|
||||
}
|
||||
|
||||
static int bcmasp_get_sset_count(struct net_device *dev, int string_set)
|
||||
{
|
||||
switch (string_set) {
|
||||
case ETH_SS_STATS:
|
||||
return BCMASP_STATS_LEN;
|
||||
default:
|
||||
return -EOPNOTSUPP;
|
||||
}
|
||||
}
|
||||
|
||||
static void bcmasp_get_strings(struct net_device *dev, u32 stringset,
|
||||
u8 *data)
|
||||
{
|
||||
unsigned int i;
|
||||
|
||||
switch (stringset) {
|
||||
case ETH_SS_STATS:
|
||||
for (i = 0; i < BCMASP_STATS_LEN; i++) {
|
||||
memcpy(data + i * ETH_GSTRING_LEN,
|
||||
bcmasp_gstrings_stats[i].stat_string,
|
||||
ETH_GSTRING_LEN);
|
||||
}
|
||||
break;
|
||||
default:
|
||||
return;
|
||||
}
|
||||
}
|
||||
|
||||
static void bcmasp_update_mib_counters(struct bcmasp_intf *intf)
|
||||
{
|
||||
unsigned int i;
|
||||
|
||||
for (i = 0; i < BCMASP_STATS_LEN; i++) {
|
||||
const struct bcmasp_stats *s;
|
||||
u32 offset, val;
|
||||
char *p;
|
||||
|
||||
s = &bcmasp_gstrings_stats[i];
|
||||
offset = bcmasp_stat_fixup_offset(intf, s);
|
||||
switch (s->type) {
|
||||
case BCMASP_STAT_SOFT:
|
||||
continue;
|
||||
case BCMASP_STAT_RX_EDPKT:
|
||||
val = rx_edpkt_core_rl(intf->parent, offset);
|
||||
break;
|
||||
case BCMASP_STAT_RX_CTRL:
|
||||
val = rx_ctrl_core_rl(intf->parent, offset);
|
||||
break;
|
||||
case BCMASP_STAT_RX_CTRL_PER_INTF:
|
||||
offset += sizeof(u32) * intf->port;
|
||||
val = rx_ctrl_core_rl(intf->parent, offset);
|
||||
break;
|
||||
default:
|
||||
continue;
|
||||
}
|
||||
p = (char *)(&intf->mib) + (i * sizeof(u32));
|
||||
put_unaligned(val, (u32 *)p);
|
||||
}
|
||||
}
|
||||
|
||||
static void bcmasp_get_ethtool_stats(struct net_device *dev,
|
||||
struct ethtool_stats *stats,
|
||||
u64 *data)
|
||||
{
|
||||
struct bcmasp_intf *intf = netdev_priv(dev);
|
||||
unsigned int i;
|
||||
char *p;
|
||||
|
||||
if (netif_running(dev))
|
||||
bcmasp_update_mib_counters(intf);
|
||||
|
||||
for (i = 0; i < BCMASP_STATS_LEN; i++) {
|
||||
p = (char *)(&intf->mib) + (i * sizeof(u32));
|
||||
data[i] = *(u32 *)p;
|
||||
}
|
||||
}
|
||||
|
||||
static void bcmasp_get_drvinfo(struct net_device *dev,
|
||||
struct ethtool_drvinfo *info)
|
||||
{
|
||||
strscpy(info->driver, "bcmasp", sizeof(info->driver));
|
||||
strscpy(info->bus_info, dev_name(dev->dev.parent),
|
||||
sizeof(info->bus_info));
|
||||
}
|
||||
|
||||
static u32 bcmasp_get_msglevel(struct net_device *dev)
|
||||
{
|
||||
struct bcmasp_intf *intf = netdev_priv(dev);
|
||||
|
||||
return intf->msg_enable;
|
||||
}
|
||||
|
||||
static void bcmasp_set_msglevel(struct net_device *dev, u32 level)
|
||||
{
|
||||
struct bcmasp_intf *intf = netdev_priv(dev);
|
||||
|
||||
intf->msg_enable = level;
|
||||
}
|
||||
|
||||
#define BCMASP_SUPPORTED_WAKE (WAKE_MAGIC | WAKE_MAGICSECURE | WAKE_FILTER)
|
||||
static void bcmasp_get_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
|
||||
{
|
||||
struct bcmasp_intf *intf = netdev_priv(dev);
|
||||
|
||||
wol->supported = BCMASP_SUPPORTED_WAKE;
|
||||
wol->wolopts = intf->wolopts;
|
||||
memset(wol->sopass, 0, sizeof(wol->sopass));
|
||||
|
||||
if (wol->wolopts & WAKE_MAGICSECURE)
|
||||
memcpy(wol->sopass, intf->sopass, sizeof(intf->sopass));
|
||||
}
|
||||
|
||||
static int bcmasp_set_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
|
||||
{
|
||||
struct bcmasp_intf *intf = netdev_priv(dev);
|
||||
struct bcmasp_priv *priv = intf->parent;
|
||||
struct device *kdev = &priv->pdev->dev;
|
||||
|
||||
if (!device_can_wakeup(kdev))
|
||||
return -EOPNOTSUPP;
|
||||
|
||||
/* Interface Specific */
|
||||
intf->wolopts = wol->wolopts;
|
||||
if (intf->wolopts & WAKE_MAGICSECURE)
|
||||
memcpy(intf->sopass, wol->sopass, sizeof(wol->sopass));
|
||||
|
||||
mutex_lock(&priv->wol_lock);
|
||||
priv->enable_wol(intf, !!intf->wolopts);
|
||||
mutex_unlock(&priv->wol_lock);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int bcmasp_flow_insert(struct net_device *dev, struct ethtool_rxnfc *cmd)
|
||||
{
|
||||
struct bcmasp_intf *intf = netdev_priv(dev);
|
||||
struct bcmasp_net_filter *nfilter;
|
||||
u32 loc = cmd->fs.location;
|
||||
bool wake = false;
|
||||
|
||||
if (cmd->fs.ring_cookie == RX_CLS_FLOW_WAKE)
|
||||
wake = true;
|
||||
|
||||
/* Currently only supports WAKE filters */
|
||||
if (!wake)
|
||||
return -EOPNOTSUPP;
|
||||
|
||||
switch (cmd->fs.flow_type & ~(FLOW_EXT | FLOW_MAC_EXT)) {
|
||||
case ETHER_FLOW:
|
||||
case IP_USER_FLOW:
|
||||
case TCP_V4_FLOW:
|
||||
case UDP_V4_FLOW:
|
||||
case TCP_V6_FLOW:
|
||||
case UDP_V6_FLOW:
|
||||
break;
|
||||
default:
|
||||
return -EOPNOTSUPP;
|
||||
}
|
||||
|
||||
/* Check if filter already exists */
|
||||
if (bcmasp_netfilt_check_dup(intf, &cmd->fs))
|
||||
return -EINVAL;
|
||||
|
||||
nfilter = bcmasp_netfilt_get_init(intf, loc, wake, true);
|
||||
if (IS_ERR(nfilter))
|
||||
return PTR_ERR(nfilter);
|
||||
|
||||
/* Return the location where we did insert the filter */
|
||||
cmd->fs.location = nfilter->hw_index;
|
||||
memcpy(&nfilter->fs, &cmd->fs, sizeof(struct ethtool_rx_flow_spec));
|
||||
|
||||
/* Since we only support wake filters, defer register programming till
|
||||
* suspend time.
|
||||
*/
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int bcmasp_flow_delete(struct net_device *dev, struct ethtool_rxnfc *cmd)
|
||||
{
|
||||
struct bcmasp_intf *intf = netdev_priv(dev);
|
||||
struct bcmasp_net_filter *nfilter;
|
||||
|
||||
nfilter = bcmasp_netfilt_get_init(intf, cmd->fs.location, false, false);
|
||||
if (IS_ERR(nfilter))
|
||||
return PTR_ERR(nfilter);
|
||||
|
||||
bcmasp_netfilt_release(intf, nfilter);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int bcmasp_flow_get(struct bcmasp_intf *intf, struct ethtool_rxnfc *cmd)
|
||||
{
|
||||
struct bcmasp_net_filter *nfilter;
|
||||
|
||||
nfilter = bcmasp_netfilt_get_init(intf, cmd->fs.location, false, false);
|
||||
if (IS_ERR(nfilter))
|
||||
return PTR_ERR(nfilter);
|
||||
|
||||
memcpy(&cmd->fs, &nfilter->fs, sizeof(nfilter->fs));
|
||||
|
||||
cmd->data = NUM_NET_FILTERS;
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int bcmasp_set_rxnfc(struct net_device *dev, struct ethtool_rxnfc *cmd)
|
||||
{
|
||||
struct bcmasp_intf *intf = netdev_priv(dev);
|
||||
int ret = -EOPNOTSUPP;
|
||||
|
||||
mutex_lock(&intf->parent->net_lock);
|
||||
|
||||
switch (cmd->cmd) {
|
||||
case ETHTOOL_SRXCLSRLINS:
|
||||
ret = bcmasp_flow_insert(dev, cmd);
|
||||
break;
|
||||
case ETHTOOL_SRXCLSRLDEL:
|
||||
ret = bcmasp_flow_delete(dev, cmd);
|
||||
break;
|
||||
default:
|
||||
break;
|
||||
}
|
||||
|
||||
mutex_unlock(&intf->parent->net_lock);
|
||||
|
||||
return ret;
|
||||
}
|
||||
|
||||
static int bcmasp_get_rxnfc(struct net_device *dev, struct ethtool_rxnfc *cmd,
|
||||
u32 *rule_locs)
|
||||
{
|
||||
struct bcmasp_intf *intf = netdev_priv(dev);
|
||||
int err = 0;
|
||||
|
||||
mutex_lock(&intf->parent->net_lock);
|
||||
|
||||
switch (cmd->cmd) {
|
||||
case ETHTOOL_GRXCLSRLCNT:
|
||||
cmd->rule_cnt = bcmasp_netfilt_get_active(intf);
|
||||
/* We support specifying rule locations */
|
||||
cmd->data |= RX_CLS_LOC_SPECIAL;
|
||||
break;
|
||||
case ETHTOOL_GRXCLSRULE:
|
||||
err = bcmasp_flow_get(intf, cmd);
|
||||
break;
|
||||
case ETHTOOL_GRXCLSRLALL:
|
||||
bcmasp_netfilt_get_all_active(intf, rule_locs, &cmd->rule_cnt);
|
||||
cmd->data = NUM_NET_FILTERS;
|
||||
break;
|
||||
default:
|
||||
err = -EOPNOTSUPP;
|
||||
break;
|
||||
}
|
||||
|
||||
mutex_unlock(&intf->parent->net_lock);
|
||||
|
||||
return err;
|
||||
}
|
||||
|
||||
void bcmasp_eee_enable_set(struct bcmasp_intf *intf, bool enable)
|
||||
{
|
||||
u32 reg;
|
||||
|
||||
reg = umac_rl(intf, UMC_EEE_CTRL);
|
||||
if (enable)
|
||||
reg |= EEE_EN;
|
||||
else
|
||||
reg &= ~EEE_EN;
|
||||
umac_wl(intf, reg, UMC_EEE_CTRL);
|
||||
|
||||
intf->eee.eee_enabled = enable;
|
||||
intf->eee.eee_active = enable;
|
||||
}
|
||||
|
||||
static int bcmasp_get_eee(struct net_device *dev, struct ethtool_eee *e)
|
||||
{
|
||||
struct bcmasp_intf *intf = netdev_priv(dev);
|
||||
struct ethtool_eee *p = &intf->eee;
|
||||
|
||||
if (!dev->phydev)
|
||||
return -ENODEV;
|
||||
|
||||
e->eee_enabled = p->eee_enabled;
|
||||
e->eee_active = p->eee_active;
|
||||
e->tx_lpi_enabled = p->tx_lpi_enabled;
|
||||
e->tx_lpi_timer = umac_rl(intf, UMC_EEE_LPI_TIMER);
|
||||
|
||||
return phy_ethtool_get_eee(dev->phydev, e);
|
||||
}
|
||||
|
||||
static int bcmasp_set_eee(struct net_device *dev, struct ethtool_eee *e)
|
||||
{
|
||||
struct bcmasp_intf *intf = netdev_priv(dev);
|
||||
struct ethtool_eee *p = &intf->eee;
|
||||
int ret;
|
||||
|
||||
if (!dev->phydev)
|
||||
return -ENODEV;
|
||||
|
||||
if (!p->eee_enabled) {
|
||||
bcmasp_eee_enable_set(intf, false);
|
||||
} else {
|
||||
ret = phy_init_eee(dev->phydev, 0);
|
||||
if (ret) {
|
||||
netif_err(intf, hw, dev,
|
||||
"EEE initialization failed: %d\n", ret);
|
||||
return ret;
|
||||
}
|
||||
|
||||
umac_wl(intf, e->tx_lpi_timer, UMC_EEE_LPI_TIMER);
|
||||
intf->eee.eee_active = ret >= 0;
|
||||
intf->eee.tx_lpi_enabled = e->tx_lpi_enabled;
|
||||
bcmasp_eee_enable_set(intf, true);
|
||||
}
|
||||
|
||||
return phy_ethtool_set_eee(dev->phydev, e);
|
||||
}
|
||||
|
||||
static void bcmasp_get_eth_mac_stats(struct net_device *dev,
|
||||
struct ethtool_eth_mac_stats *mac_stats)
|
||||
{
|
||||
struct bcmasp_intf *intf = netdev_priv(dev);
|
||||
|
||||
mac_stats->FramesTransmittedOK = umac_rl(intf, UMC_GTPOK);
|
||||
mac_stats->SingleCollisionFrames = umac_rl(intf, UMC_GTSCL);
|
||||
mac_stats->MultipleCollisionFrames = umac_rl(intf, UMC_GTMCL);
|
||||
mac_stats->FramesReceivedOK = umac_rl(intf, UMC_GRPOK);
|
||||
mac_stats->FrameCheckSequenceErrors = umac_rl(intf, UMC_GRFCS);
|
||||
mac_stats->AlignmentErrors = umac_rl(intf, UMC_GRALN);
|
||||
mac_stats->OctetsTransmittedOK = umac_rl(intf, UMC_GTBYT);
|
||||
mac_stats->FramesWithDeferredXmissions = umac_rl(intf, UMC_GTDRF);
|
||||
mac_stats->LateCollisions = umac_rl(intf, UMC_GTLCL);
|
||||
mac_stats->FramesAbortedDueToXSColls = umac_rl(intf, UMC_GTXCL);
|
||||
mac_stats->OctetsReceivedOK = umac_rl(intf, UMC_GRBYT);
|
||||
mac_stats->MulticastFramesXmittedOK = umac_rl(intf, UMC_GTMCA);
|
||||
mac_stats->BroadcastFramesXmittedOK = umac_rl(intf, UMC_GTBCA);
|
||||
mac_stats->FramesWithExcessiveDeferral = umac_rl(intf, UMC_GTEDF);
|
||||
mac_stats->MulticastFramesReceivedOK = umac_rl(intf, UMC_GRMCA);
|
||||
mac_stats->BroadcastFramesReceivedOK = umac_rl(intf, UMC_GRBCA);
|
||||
}
|
||||
|
||||
static const struct ethtool_rmon_hist_range bcmasp_rmon_ranges[] = {
|
||||
{ 0, 64},
|
||||
{ 65, 127},
|
||||
{ 128, 255},
|
||||
{ 256, 511},
|
||||
{ 512, 1023},
|
||||
{ 1024, 1518},
|
||||
{ 1519, 1522},
|
||||
{}
|
||||
};
|
||||
|
||||
static void bcmasp_get_rmon_stats(struct net_device *dev,
|
||||
struct ethtool_rmon_stats *rmon_stats,
|
||||
const struct ethtool_rmon_hist_range **ranges)
|
||||
{
|
||||
struct bcmasp_intf *intf = netdev_priv(dev);
|
||||
|
||||
*ranges = bcmasp_rmon_ranges;
|
||||
|
||||
rmon_stats->undersize_pkts = umac_rl(intf, UMC_RRUND);
|
||||
rmon_stats->oversize_pkts = umac_rl(intf, UMC_GROVR);
|
||||
rmon_stats->fragments = umac_rl(intf, UMC_RRFRG);
|
||||
rmon_stats->jabbers = umac_rl(intf, UMC_GRJBR);
|
||||
|
||||
rmon_stats->hist[0] = umac_rl(intf, UMC_GR64);
|
||||
rmon_stats->hist[1] = umac_rl(intf, UMC_GR127);
|
||||
rmon_stats->hist[2] = umac_rl(intf, UMC_GR255);
|
||||
rmon_stats->hist[3] = umac_rl(intf, UMC_GR511);
|
||||
rmon_stats->hist[4] = umac_rl(intf, UMC_GR1023);
|
||||
rmon_stats->hist[5] = umac_rl(intf, UMC_GR1518);
|
||||
rmon_stats->hist[6] = umac_rl(intf, UMC_GRMGV);
|
||||
|
||||
rmon_stats->hist_tx[0] = umac_rl(intf, UMC_TR64);
|
||||
rmon_stats->hist_tx[1] = umac_rl(intf, UMC_TR127);
|
||||
rmon_stats->hist_tx[2] = umac_rl(intf, UMC_TR255);
|
||||
rmon_stats->hist_tx[3] = umac_rl(intf, UMC_TR511);
|
||||
rmon_stats->hist_tx[4] = umac_rl(intf, UMC_TR1023);
|
||||
rmon_stats->hist_tx[5] = umac_rl(intf, UMC_TR1518);
|
||||
rmon_stats->hist_tx[6] = umac_rl(intf, UMC_TRMGV);
|
||||
}
|
||||
|
||||
static void bcmasp_get_eth_ctrl_stats(struct net_device *dev,
|
||||
struct ethtool_eth_ctrl_stats *ctrl_stats)
|
||||
{
|
||||
struct bcmasp_intf *intf = netdev_priv(dev);
|
||||
|
||||
ctrl_stats->MACControlFramesTransmitted = umac_rl(intf, UMC_GTXCF);
|
||||
ctrl_stats->MACControlFramesReceived = umac_rl(intf, UMC_GRXCF);
|
||||
ctrl_stats->UnsupportedOpcodesReceived = umac_rl(intf, UMC_GRXUO);
|
||||
}
|
||||
|
||||
const struct ethtool_ops bcmasp_ethtool_ops = {
|
||||
.get_drvinfo = bcmasp_get_drvinfo,
|
||||
.get_link = ethtool_op_get_link,
|
||||
.get_link_ksettings = phy_ethtool_get_link_ksettings,
|
||||
.set_link_ksettings = phy_ethtool_set_link_ksettings,
|
||||
.get_msglevel = bcmasp_get_msglevel,
|
||||
.set_msglevel = bcmasp_set_msglevel,
|
||||
.get_wol = bcmasp_get_wol,
|
||||
.set_wol = bcmasp_set_wol,
|
||||
.get_rxnfc = bcmasp_get_rxnfc,
|
||||
.set_rxnfc = bcmasp_set_rxnfc,
|
||||
.set_eee = bcmasp_set_eee,
|
||||
.get_eee = bcmasp_get_eee,
|
||||
.get_eth_mac_stats = bcmasp_get_eth_mac_stats,
|
||||
.get_rmon_stats = bcmasp_get_rmon_stats,
|
||||
.get_eth_ctrl_stats = bcmasp_get_eth_ctrl_stats,
|
||||
.get_strings = bcmasp_get_strings,
|
||||
.get_ethtool_stats = bcmasp_get_ethtool_stats,
|
||||
.get_sset_count = bcmasp_get_sset_count,
|
||||
};
|
||||
File diff suppressed because it is too large
Load Diff
|
|
@ -0,0 +1,257 @@
|
|||
/* SPDX-License-Identifier: GPL-2.0 */
|
||||
#ifndef __BCMASP_INTF_DEFS_H
|
||||
#define __BCMASP_INTF_DEFS_H
|
||||
|
||||
#define UMC_OFFSET(intf) \
|
||||
((((intf)->port) * 0x800) + 0xc000)
|
||||
#define UMC_CMD 0x008
|
||||
#define UMC_CMD_TX_EN BIT(0)
|
||||
#define UMC_CMD_RX_EN BIT(1)
|
||||
#define UMC_CMD_SPEED_SHIFT 0x2
|
||||
#define UMC_CMD_SPEED_MASK 0x3
|
||||
#define UMC_CMD_SPEED_10 0x0
|
||||
#define UMC_CMD_SPEED_100 0x1
|
||||
#define UMC_CMD_SPEED_1000 0x2
|
||||
#define UMC_CMD_SPEED_2500 0x3
|
||||
#define UMC_CMD_PROMISC BIT(4)
|
||||
#define UMC_CMD_PAD_EN BIT(5)
|
||||
#define UMC_CMD_CRC_FWD BIT(6)
|
||||
#define UMC_CMD_PAUSE_FWD BIT(7)
|
||||
#define UMC_CMD_RX_PAUSE_IGNORE BIT(8)
|
||||
#define UMC_CMD_TX_ADDR_INS BIT(9)
|
||||
#define UMC_CMD_HD_EN BIT(10)
|
||||
#define UMC_CMD_SW_RESET BIT(13)
|
||||
#define UMC_CMD_LCL_LOOP_EN BIT(15)
|
||||
#define UMC_CMD_AUTO_CONFIG BIT(22)
|
||||
#define UMC_CMD_CNTL_FRM_EN BIT(23)
|
||||
#define UMC_CMD_NO_LEN_CHK BIT(24)
|
||||
#define UMC_CMD_RMT_LOOP_EN BIT(25)
|
||||
#define UMC_CMD_PRBL_EN BIT(27)
|
||||
#define UMC_CMD_TX_PAUSE_IGNORE BIT(28)
|
||||
#define UMC_CMD_TX_RX_EN BIT(29)
|
||||
#define UMC_CMD_RUNT_FILTER_DIS BIT(30)
|
||||
#define UMC_MAC0 0x0c
|
||||
#define UMC_MAC1 0x10
|
||||
#define UMC_FRM_LEN 0x14
|
||||
#define UMC_EEE_CTRL 0x64
|
||||
#define EN_LPI_RX_PAUSE BIT(0)
|
||||
#define EN_LPI_TX_PFC BIT(1)
|
||||
#define EN_LPI_TX_PAUSE BIT(2)
|
||||
#define EEE_EN BIT(3)
|
||||
#define RX_FIFO_CHECK BIT(4)
|
||||
#define EEE_TX_CLK_DIS BIT(5)
|
||||
#define DIS_EEE_10M BIT(6)
|
||||
#define LP_IDLE_PREDICTION_MODE BIT(7)
|
||||
#define UMC_EEE_LPI_TIMER 0x68
|
||||
#define UMC_PAUSE_CNTRL 0x330
|
||||
#define UMC_TX_FLUSH 0x334
|
||||
#define UMC_GR64 0x400
|
||||
#define UMC_GR127 0x404
|
||||
#define UMC_GR255 0x408
|
||||
#define UMC_GR511 0x40c
|
||||
#define UMC_GR1023 0x410
|
||||
#define UMC_GR1518 0x414
|
||||
#define UMC_GRMGV 0x418
|
||||
#define UMC_GR2047 0x41c
|
||||
#define UMC_GR4095 0x420
|
||||
#define UMC_GR9216 0x424
|
||||
#define UMC_GRPKT 0x428
|
||||
#define UMC_GRBYT 0x42c
|
||||
#define UMC_GRMCA 0x430
|
||||
#define UMC_GRBCA 0x434
|
||||
#define UMC_GRFCS 0x438
|
||||
#define UMC_GRXCF 0x43c
|
||||
#define UMC_GRXPF 0x440
|
||||
#define UMC_GRXUO 0x444
|
||||
#define UMC_GRALN 0x448
|
||||
#define UMC_GRFLR 0x44c
|
||||
#define UMC_GRCDE 0x450
|
||||
#define UMC_GRFCR 0x454
|
||||
#define UMC_GROVR 0x458
|
||||
#define UMC_GRJBR 0x45c
|
||||
#define UMC_GRMTUE 0x460
|
||||
#define UMC_GRPOK 0x464
|
||||
#define UMC_GRUC 0x468
|
||||
#define UMC_GRPPP 0x46c
|
||||
#define UMC_GRMCRC 0x470
|
||||
#define UMC_TR64 0x480
|
||||
#define UMC_TR127 0x484
|
||||
#define UMC_TR255 0x488
|
||||
#define UMC_TR511 0x48c
|
||||
#define UMC_TR1023 0x490
|
||||
#define UMC_TR1518 0x494
|
||||
#define UMC_TRMGV 0x498
|
||||
#define UMC_TR2047 0x49c
|
||||
#define UMC_TR4095 0x4a0
|
||||
#define UMC_TR9216 0x4a4
|
||||
#define UMC_GTPKT 0x4a8
|
||||
#define UMC_GTMCA 0x4ac
|
||||
#define UMC_GTBCA 0x4b0
|
||||
#define UMC_GTXPF 0x4b4
|
||||
#define UMC_GTXCF 0x4b8
|
||||
#define UMC_GTFCS 0x4bc
|
||||
#define UMC_GTOVR 0x4c0
|
||||
#define UMC_GTDRF 0x4c4
|
||||
#define UMC_GTEDF 0x4c8
|
||||
#define UMC_GTSCL 0x4cc
|
||||
#define UMC_GTMCL 0x4d0
|
||||
#define UMC_GTLCL 0x4d4
|
||||
#define UMC_GTXCL 0x4d8
|
||||
#define UMC_GTFRG 0x4dc
|
||||
#define UMC_GTNCL 0x4e0
|
||||
#define UMC_GTJBR 0x4e4
|
||||
#define UMC_GTBYT 0x4e8
|
||||
#define UMC_GTPOK 0x4ec
|
||||
#define UMC_GTUC 0x4f0
|
||||
#define UMC_RRPKT 0x500
|
||||
#define UMC_RRUND 0x504
|
||||
#define UMC_RRFRG 0x508
|
||||
#define UMC_RRBYT 0x50c
|
||||
#define UMC_MIB_CNTRL 0x580
|
||||
#define UMC_MIB_CNTRL_RX_CNT_RST BIT(0)
|
||||
#define UMC_MIB_CNTRL_RUNT_CNT_RST BIT(1)
|
||||
#define UMC_MIB_CNTRL_TX_CNT_RST BIT(2)
|
||||
#define UMC_RX_MAX_PKT_SZ 0x608
|
||||
#define UMC_MPD_CTRL 0x620
|
||||
#define UMC_MPD_CTRL_MPD_EN BIT(0)
|
||||
#define UMC_MPD_CTRL_PSW_EN BIT(27)
|
||||
#define UMC_PSW_MS 0x624
|
||||
#define UMC_PSW_LS 0x628
|
||||
|
||||
#define UMAC2FB_OFFSET_2_1 0x9f044
|
||||
#define UMAC2FB_OFFSET 0x9f03c
|
||||
#define UMAC2FB_CFG 0x0
|
||||
#define UMAC2FB_CFG_OPUT_EN BIT(0)
|
||||
#define UMAC2FB_CFG_VLAN_EN BIT(1)
|
||||
#define UMAC2FB_CFG_SNAP_EN BIT(2)
|
||||
#define UMAC2FB_CFG_BCM_TG_EN BIT(3)
|
||||
#define UMAC2FB_CFG_IPUT_EN BIT(4)
|
||||
#define UMAC2FB_CFG_CHID_SHIFT 8
|
||||
#define UMAC2FB_CFG_OK_SEND_SHIFT 24
|
||||
#define UMAC2FB_CFG_DEFAULT_EN \
|
||||
(UMAC2FB_CFG_OPUT_EN | UMAC2FB_CFG_VLAN_EN \
|
||||
| UMAC2FB_CFG_SNAP_EN | UMAC2FB_CFG_IPUT_EN)
|
||||
|
||||
#define RGMII_OFFSET(intf) \
|
||||
((((intf)->port) * 0x100) + 0xd000)
|
||||
#define RGMII_EPHY_CNTRL 0x00
|
||||
#define RGMII_EPHY_CFG_IDDQ_BIAS BIT(0)
|
||||
#define RGMII_EPHY_CFG_EXT_PWRDOWN BIT(1)
|
||||
#define RGMII_EPHY_CFG_FORCE_DLL_EN BIT(2)
|
||||
#define RGMII_EPHY_CFG_IDDQ_GLOBAL BIT(3)
|
||||
#define RGMII_EPHY_CK25_DIS BIT(4)
|
||||
#define RGMII_EPHY_RESET BIT(7)
|
||||
#define RGMII_OOB_CNTRL 0x0c
|
||||
#define RGMII_LINK BIT(4)
|
||||
#define RGMII_OOB_DIS BIT(5)
|
||||
#define RGMII_MODE_EN BIT(6)
|
||||
#define RGMII_ID_MODE_DIS BIT(16)
|
||||
|
||||
#define RGMII_PORT_CNTRL 0x60
|
||||
#define RGMII_PORT_MODE_EPHY 0
|
||||
#define RGMII_PORT_MODE_GPHY 1
|
||||
#define RGMII_PORT_MODE_EXT_EPHY 2
|
||||
#define RGMII_PORT_MODE_EXT_GPHY 3
|
||||
#define RGMII_PORT_MODE_EXT_RVMII 4
|
||||
#define RGMII_PORT_MODE_MASK GENMASK(2, 0)
|
||||
|
||||
#define RGMII_SYS_LED_CNTRL 0x74
|
||||
#define RGMII_SYS_LED_CNTRL_LINK_OVRD BIT(15)
|
||||
|
||||
#define TX_SPB_DMA_OFFSET(intf) \
|
||||
((((intf)->channel) * 0x30) + 0x48180)
|
||||
#define TX_SPB_DMA_READ 0x00
|
||||
#define TX_SPB_DMA_BASE 0x08
|
||||
#define TX_SPB_DMA_END 0x10
|
||||
#define TX_SPB_DMA_VALID 0x18
|
||||
#define TX_SPB_DMA_FIFO_CTRL 0x20
|
||||
#define TX_SPB_DMA_FIFO_FLUSH BIT(0)
|
||||
#define TX_SPB_DMA_FIFO_STATUS 0x24
|
||||
|
||||
#define TX_SPB_CTRL_OFFSET(intf) \
|
||||
((((intf)->channel) * 0x68) + 0x49340)
|
||||
#define TX_SPB_CTRL_ENABLE 0x0
|
||||
#define TX_SPB_CTRL_ENABLE_EN BIT(0)
|
||||
#define TX_SPB_CTRL_XF_CTRL2 0x20
|
||||
#define TX_SPB_CTRL_XF_BID_SHIFT 16
|
||||
|
||||
#define TX_SPB_TOP_OFFSET(intf) \
|
||||
((((intf)->channel) * 0x1c) + 0x4a0e0)
|
||||
#define TX_SPB_TOP_BLKOUT 0x0
|
||||
#define TX_SPB_TOP_SPRE_BW_CTRL 0x4
|
||||
|
||||
#define TX_EPKT_C_OFFSET(intf) \
|
||||
((((intf)->channel) * 0x120) + 0x40900)
|
||||
#define TX_EPKT_C_CFG_MISC 0x0
|
||||
#define TX_EPKT_C_CFG_MISC_EN BIT(0)
|
||||
#define TX_EPKT_C_CFG_MISC_PT BIT(1)
|
||||
#define TX_EPKT_C_CFG_MISC_PS_SHIFT 14
|
||||
#define TX_EPKT_C_CFG_MISC_FD_SHIFT 20
|
||||
|
||||
#define TX_PAUSE_CTRL_OFFSET(intf) \
|
||||
((((intf)->channel * 0xc) + 0x49a20))
|
||||
#define TX_PAUSE_MAP_VECTOR 0x8
|
||||
|
||||
#define RX_EDPKT_DMA_OFFSET(intf) \
|
||||
((((intf)->channel) * 0x38) + 0x9ca00)
|
||||
#define RX_EDPKT_DMA_WRITE 0x00
|
||||
#define RX_EDPKT_DMA_READ 0x08
|
||||
#define RX_EDPKT_DMA_BASE 0x10
|
||||
#define RX_EDPKT_DMA_END 0x18
|
||||
#define RX_EDPKT_DMA_VALID 0x20
|
||||
#define RX_EDPKT_DMA_FULLNESS 0x28
|
||||
#define RX_EDPKT_DMA_MIN_THRES 0x2c
|
||||
#define RX_EDPKT_DMA_CH_XONOFF 0x30
|
||||
|
||||
#define RX_EDPKT_CFG_OFFSET(intf) \
|
||||
((((intf)->channel) * 0x70) + 0x9c600)
|
||||
#define RX_EDPKT_CFG_CFG0 0x0
|
||||
#define RX_EDPKT_CFG_CFG0_DBUF_SHIFT 9
|
||||
#define RX_EDPKT_CFG_CFG0_RBUF 0x0
|
||||
#define RX_EDPKT_CFG_CFG0_RBUF_4K 0x1
|
||||
#define RX_EDPKT_CFG_CFG0_BUF_4K 0x2
|
||||
/* EFRM STUFF, 0 = no byte stuff, 1 = two byte stuff */
|
||||
#define RX_EDPKT_CFG_CFG0_EFRM_STUF BIT(11)
|
||||
#define RX_EDPKT_CFG_CFG0_BALN_SHIFT 12
|
||||
#define RX_EDPKT_CFG_CFG0_NO_ALN 0
|
||||
#define RX_EDPKT_CFG_CFG0_4_ALN 2
|
||||
#define RX_EDPKT_CFG_CFG0_64_ALN 6
|
||||
#define RX_EDPKT_RING_BUFFER_WRITE 0x38
|
||||
#define RX_EDPKT_RING_BUFFER_READ 0x40
|
||||
#define RX_EDPKT_RING_BUFFER_BASE 0x48
|
||||
#define RX_EDPKT_RING_BUFFER_END 0x50
|
||||
#define RX_EDPKT_RING_BUFFER_VALID 0x58
|
||||
#define RX_EDPKT_CFG_ENABLE 0x6c
|
||||
#define RX_EDPKT_CFG_ENABLE_EN BIT(0)
|
||||
|
||||
#define RX_SPB_DMA_OFFSET(intf) \
|
||||
((((intf)->channel) * 0x30) + 0xa0000)
|
||||
#define RX_SPB_DMA_READ 0x00
|
||||
#define RX_SPB_DMA_BASE 0x08
|
||||
#define RX_SPB_DMA_END 0x10
|
||||
#define RX_SPB_DMA_VALID 0x18
|
||||
#define RX_SPB_DMA_FIFO_CTRL 0x20
|
||||
#define RX_SPB_DMA_FIFO_FLUSH BIT(0)
|
||||
#define RX_SPB_DMA_FIFO_STATUS 0x24
|
||||
|
||||
#define RX_SPB_CTRL_OFFSET(intf) \
|
||||
((((intf)->channel - 6) * 0x68) + 0xa1000)
|
||||
#define RX_SPB_CTRL_ENABLE 0x00
|
||||
#define RX_SPB_CTRL_ENABLE_EN BIT(0)
|
||||
|
||||
#define RX_PAUSE_CTRL_OFFSET(intf) \
|
||||
((((intf)->channel - 6) * 0x4) + 0xa1138)
|
||||
#define RX_PAUSE_MAP_VECTOR 0x00
|
||||
|
||||
#define RX_SPB_TOP_CTRL_OFFSET(intf) \
|
||||
((((intf)->channel - 6) * 0x14) + 0xa2000)
|
||||
#define RX_SPB_TOP_BLKOUT 0x00
|
||||
|
||||
#define NUM_4K_BUFFERS 32
|
||||
#define RING_BUFFER_SIZE (PAGE_SIZE * NUM_4K_BUFFERS)
|
||||
|
||||
#define DESC_RING_COUNT (64 * NUM_4K_BUFFERS)
|
||||
#define DESC_SIZE 16
|
||||
#define DESC_RING_SIZE (DESC_RING_COUNT * DESC_SIZE)
|
||||
|
||||
#endif
|
||||
|
|
@ -334,6 +334,8 @@ static SIMPLE_DEV_PM_OPS(unimac_mdio_pm_ops,
|
|||
unimac_mdio_suspend, unimac_mdio_resume);
|
||||
|
||||
static const struct of_device_id unimac_mdio_ids[] = {
|
||||
{ .compatible = "brcm,asp-v2.1-mdio", },
|
||||
{ .compatible = "brcm,asp-v2.0-mdio", },
|
||||
{ .compatible = "brcm,genet-mdio-v5", },
|
||||
{ .compatible = "brcm,genet-mdio-v4", },
|
||||
{ .compatible = "brcm,genet-mdio-v3", },
|
||||
|
|
|
|||
|
|
@ -913,6 +913,7 @@ static struct phy_driver bcm7xxx_driver[] = {
|
|||
BCM7XXX_28NM_GPHY(PHY_ID_BCM7278, "Broadcom BCM7278"),
|
||||
BCM7XXX_28NM_GPHY(PHY_ID_BCM7364, "Broadcom BCM7364"),
|
||||
BCM7XXX_28NM_GPHY(PHY_ID_BCM7366, "Broadcom BCM7366"),
|
||||
BCM7XXX_16NM_EPHY(PHY_ID_BCM74165, "Broadcom BCM74165"),
|
||||
BCM7XXX_28NM_GPHY(PHY_ID_BCM74371, "Broadcom BCM74371"),
|
||||
BCM7XXX_28NM_GPHY(PHY_ID_BCM7439, "Broadcom BCM7439"),
|
||||
BCM7XXX_28NM_GPHY(PHY_ID_BCM7439_2, "Broadcom BCM7439 (2)"),
|
||||
|
|
|
|||
|
|
@ -44,6 +44,7 @@
|
|||
#define PHY_ID_BCM7366 0x600d8490
|
||||
#define PHY_ID_BCM7346 0x600d8650
|
||||
#define PHY_ID_BCM7362 0x600d84b0
|
||||
#define PHY_ID_BCM74165 0x359052c0
|
||||
#define PHY_ID_BCM7425 0x600d86b0
|
||||
#define PHY_ID_BCM7429 0x600d8730
|
||||
#define PHY_ID_BCM7435 0x600d8750
|
||||
|
|
|
|||
Loading…
Reference in New Issue